Jobs
>
Santa Clara

    SOC Senior Physical Design Engineer - Santa Clara, United States - Intel

    Intel
    Intel Santa Clara, United States

    1 week ago

    Intel background
    Description

    Job Description

    Do Something Wonderful
    Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel ) or the links below

    • Life at Intel )
    • Diversity at Intel )

    The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge.

    We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform data-center and AI ecosystems.


    The Senior Physical Design Engineer in NEX:

    • Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
    • Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
    • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
    • Analyzes results and makes recommendations to fix violations for current and future product architecture.
    • Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
    • Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
    In addition to the qualifications listed below the ideal candidate will also have the following traits:

    • Willingness to multi-task and manage several activities at once.
    • Strong attention to detail and organizational skills to track and communicate direction/status.
    • Willingness to work in an unstructured start-up like environment with minimal supervision.
    • Strong problem-solving abilities to help drive resolution of unforeseen issues.
    • Excellent communication skills both verbally and non-verbally in an effective, professional, clear, and honest manner with team members, customers, and leadership.
    • Able to deal with ambiguity, cope with change and can comfortably handle risk and uncertainty.
    • Be self-driven and motivated.
    • Willingness to lead a highly matrixed, cross-organizational team directly tied to the development, implementation and/or upgrade of technology or products for external customers.

    Qualifications

    What we need to see (Minimum Qualifications):

    • Candidate must have a bachelor's degree in Electrical Engineering, Computer Engineering, CS with 8 years OR Master's degree in Computer science/Electrical or Computer Engineering with 6 years of experience in:
    • 5 years experience with Physical design and integration/execution of complex SOCs/ASICs in 5nm and below.
    • 5 years experience with microelectronic designs, semiconductor device physics, the CMOS process, and physical layout.
    • 5 years' experience in tools such as Design Compiler, ICC2/Innovus, Primetime, etc.
    • 4 years' experience of DFT, DFM, clocking, FEV, top-down and bottom-up design flows.
    • 4 years' experience scripting in PERL, TCL.

    How to Stand Out (Preferred Qualifications):

    • Experience working with advanced process nodes such as 5nm and below
    • Expert in physical design tools such as Design Compiler, Fusion Compiler, and Conformal.
    • Experience in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification.
    • Knowledge of floor planning, pin placement, and SOC integration.
    • Experience with various types of external interfaces, such as DDR, PCIe, and similar
    • Experience as a team lead.
    Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research

    Amazing Benefits
    Here at Intel, we invest in our people.

    Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.

    Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program.


    Find more information about our Amazing Benefits here:

    Inside this Business Group

    The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership.

    It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.


    Posting Statement

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


    Benefits
    We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. )

    Annual Salary Range for jobs which could be performed in US, California:
    $162,041.00-$259,425.00
    *Salary range dependent on a number of factors including location and experience

    Working Model

    This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.


    In certain circumstances the work model may change to accommodate business needs.
  • Dawar Consulting, Inc.

    Mechanical Design Engineer 4

    20 hours ago

    Dawar Consulting, Inc. Milpitas, United States

    Our client, a world leader in the semiconductor industry, is looking for a "Mechanical Design Engineer 4". · Job Title: Mechanical Design Engineer 4 · Shift Hours: 9 AM- 5 PM · Job Duration: Long-term Contract on W2 (Onsite) · Location: Milpitas, CA · Company Benefits: · Health ...

  • NVIDIA Corporation

    Design Engineer/Senior Design Engineer

    1 week ago

    NVIDIA Corporation Santa Clara, CA, United States

    Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer · Apply locations US, CA, Santa Clara time type Full time posted on Posted 5 Days Ago job requisition id JR NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's lea ...

  • NVIDIA Corporation

    Design Engineer/Senior Design Engineer

    5 days ago

    NVIDIA Corporation Santa Clara, CA, United States

    Senior Design Engineer, Coherent High Speed Interconnect page is loaded Senior Design Engineer, Coherent High Speed Interconnect · Apply locations US, CA, Santa Clara US, MA, Westford US, TX, Remote US, CA, Remote US, Remote time type Full time posted on Posted 2 Days Ago job re ...

  • Phoenix Ventures

    Project engineer for CAD design

    5 days ago

    Phoenix Ventures Moffett, United States

    What can you expect? · You will plan spray experiments and design spray dryer systems · You will communicate with customers and provide advice · You will create quotes in collaboration with sales · You will create components in SAP and generate bills of materials · You will creat ...

  • CYNET SYSTEMS

    Design Engineer/Senior Design Engineer

    4 days ago

    CYNET SYSTEMS Santa Clara, CA, United States

    Job Description: · Pay Range $50.64hr - $75.92hr · Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff. · Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automatin ...

  • Intel Corporation

    Product Engineer/Design Engineer

    1 week ago

    Intel Corporation Santa Clara, CA, United States

    Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. Join us, because at Intel, we are building a better tomorrow. Intel NEX Cloud ...

  • Innogrit

    Design Engineer

    2 days ago

    Innogrit San Jose, United States

    Job Description · Job Description Salary: DOE · Job description · Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs. · Implement design modules using hardware description language (HDL). · Design schemes for multi-clock domain crossin ...

  • Cepton Technologies

    Design Engineer/Senior Design Engineer

    5 days ago

    Cepton Technologies San Jose, CA, United States

    Cepton (Nasdaq: CPTN), a leading intelligent lidar solution provider, is seeking a seasoned Senior ASIC Design Engineer who is passionate about solving challenges to join us and support the development of Lidar products. Working closely with our Director of ASIC Engineering and p ...

  • USA Tech Recruitment

    Design Engineer/Senior Design Engineer

    4 days ago

    USA Tech Recruitment San Jose, CA, United States

    Are you an ASIC Design Engineer that is on the market for a new opportunity at a highly funded and expanding startup, working on cutting edge projects at the forefront of autonomous driving and AI as a whole? · At European Recruitment we are working alongside a widely successful ...

  • Experis

    RTL Design Engineer

    2 days ago

    Experis Santa Clara, United States contract

    Location: Onsite San Jose, CA · JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for lint ...

  • TekWissen ®

    RTL Design Engineer

    1 week ago

    TekWissen ® Santa Clara, United States

    Job Title: RTL Design Engineer - Senior · Work Location: Santa Clara, CA 95054 · Duration: 12 Months · Work Type: Contract · Job Type: Onsite · Pay Rate: $80 /Hourly/W2 · Overview: · TekWissen Group is a workforce management provider throughout the USA and many other countr ...

  • Mirafra Technologies

    Design Verification Engineer

    2 days ago

    Mirafra Technologies Santa Clara, United States

    Looking to add DV Engineers in Irvine, San Diego and Santa Clara. · On going needs additional 10 engineers in team. · Position detail: SOC verification · Experience level : 5-20 years · Architect block and full-chip verification environments using HVLs and constrained random ...

  • Capgemini Engineering

    Design Verification Engineer

    5 days ago

    Capgemini Engineering Santa Clara, United States

    We are seeking a Design Verification Engineer with below skills. · Total 10 years of experience in UVM based verification. · System Verilog assertions experience. · Familiarity with C/C++ model integration in verification environments. · Debug skills at IP and subsystem level. · ...

  • LanceSoft, Inc.

    RTL Design Engineer

    3 days ago

    LanceSoft, Inc. Santa Clara, United States

    KEY RESPONSIBILITIES: · • Microarchitecture development of IP subsystems · • Perform RTL design of digital components. · • Work with functional verification team to meet coverage and quality standards. · • Analyze/fix Lint and CDC errors of the components. · • Guarantee quality/ ...

  • Celestial AI

    Mechanical Design Engineer

    2 days ago

    Celestial AI Santa Clara, United States

    About Celestial AIAs the industry strives to meet the demands of the AI workloads, bottlenecks in data transfers between processors and memory have hindered progress. The Photonic Fabric based Memory Fabric provides an optically scalable solution to the 'Memory Wall' problem, ena ...

  • Nvidia

    Senior Design Engineer

    5 days ago

    Nvidia Santa Clara, CA, United States

    We are now looking for a Senior Hardware Design Engineer for our Tegra group:NVIDIA is seeking passionate Senior Hardware Design Engineers to architect, design and verify the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifacet ...

  • Omni Vision Inc

    SoC Design Engineer

    2 days ago

    Omni Vision Inc Santa Clara, United States

    · Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation. Work closely with back-end team in floor-planning, timing closure and DFT. Conduct image sensor array/analog related timing control design and STA. Perform ...

  • Omni Vision Inc

    SoC Design Engineer

    3 days ago

    Omni Vision Inc Santa Clara, United States

    Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation. Work closely with back-end team in floor-planning, timing closure and DFT. Conduct image sensor array/analog related timing control design and STA. Perform chi ...

  • Diverse Lynx

    Physical Design Engineer

    2 days ago

    Diverse Lynx Santa Clara, United States

    Physical Design Engineer (8-15 Years Experience) Work Location - Santa Clara CA USA · Customer: TechMahindra · Job Description: · As a Physical Design Engineer, you will play a crucial role in the RTL to GDS flow, including Synthesis and Place & Route (PNR). You will utilize tool ...

  • Broadcom Corporation

    Design Engineer

    2 days ago

    Broadcom Corporation San Jose, United States

    Please Note: · 1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Broadcom's Timing Sign-Off g ...