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Principal Design Verification Engineer - Maine, United States - Cadence Design Systems
Description
Principal Design Verification Engineer page is loadedPrincipal Design Verification Engineer
Apply
locations
BANGALORE
time type
Full time
posted on
Posted Yesterday
job requisition id
R46063
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
6+ years of Design Verification experience with SV/UVM
Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
Design Verification experience verifying complex designs and leading projects from concept to verification closure.
Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
We're doing work that matters. Help us solve what others can't.
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