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    Physical Design Engineer - Phoenix, United States - Mastech Digital

    Mastech Digital
    Mastech Digital Phoenix, United States

    3 weeks ago

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    Description

    Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Physical Design Engineer for our client in the IT-Services domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position, and the client is looking for someone to start immediately.

    Duration: 6+ Months Contract

    Location: Phoenix, AZ

    Role: Physical Design Engineer

    Primary Skills: Engineering

    Role Description: As a Physical Design Engineer, you must have at least 8+ years of experience. Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices.

    Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms.

    Work across the entire silicon design lifecycle, including system architecture, design verification, RTL digital design, physical design, design for test (DFT), and Emulation.

    BS in Computer Science or Electrical Engineering

    3-7 years experience in semiconductor design and development.

    Must-Have Skills:

    3-7 years of experience required for each skill.

    Electrical Engineering

    Electronic Design Automation (EDA)

    Semiconductor Design & Development

    Nice-To-Have Skills:

    Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.

    Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors.

    Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.

    Responsibilities:

    Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis, power analysis, IR Drop, EM, in advanced technology nodes

    Resolve power issues related to physical design, identify potential low power solutions, drive execution and methodology improvements.

    Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design.

    Heres what you need:

    A minimum of three years of experience with:

    o RTL2GDSllon advanced technology nodes (7nm and below)

    o Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.

    o Power constraints generation and validation, power analysis, interface with power integrity analysis tools.

    o TCL, Python and/or Perl programming

    o EDA tools like DesignCompiler/Genus, Primetime/PrimePower, ICC2/Innovus, Redhawk/Voltus

    Bachelors Degree or equivalent (12 years) work experience (If an, Associates Degree with 6 years of work experience)

    Bonus points if:

    Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.

    Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors

    Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.

    Education: Bachelors degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent

    Experience: Minimum 8+ years of experience

    Relocation: This position will not cover relocation expenses

    Travel: No

    Local Preferred: Yes

    Note: Must be able to work on a W2 basis (No C2C)

    Recruiter Name: Aakash Chauhan

    Recruiter Phone: Ext: 2842)

    Equal Employment Opportunity

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