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    ASIC Digital Design, Staff Engineer - Sunnyvale, United States - Synopsys

    Synopsys
    Synopsys Sunnyvale, United States

    2 weeks ago

    Default job background
    Description

    Senior RTL Design Engineer



    50213BR

    USA - California - Mountain View/Sunnyvale

    Job Description and Requirements

    Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

    At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

    Senior RTL Design Engineer

    Synopsys is seeking a talented RTL Design Engineer and an expert in microarchitecture, RTL development for our next-generation ARC-V processor IP. Synopsys ARC-V processors IP is based on the open-source standard RISC-V instruction set architecture. The ideal candidate is experienced in the microprocessor development process, resolution of critical problems, and has a consistent track record of delivering timely and high-quality products. Cutting edge experience in IP architecture and design, utilizing the latest process technologies, is preferred.

    Responsibilities

    • Working closely with architects to develop micro-architecture and hardware specifications for the design blocks for ARC-V processor IP.
    • Developing RTL code for the design blocks with PPA considerations
    • Carrying out Linting, CDC, RDC, Synthesis and Timing Analysis of design blocks
    • Work closely with verification team to review test plans and setting the sign-off criteria for the design and verification activities
    • Interact and collaborate with various stake holders in the project (in areas related to Verification, SW, DFT, Physical design, Prototyping.. etc)
    Qualifications / Skills Desired
    • Bachelors of Science in Computer, Electrical Engineering or similar
    • 5+ years experience in ASIC digital design domain
    • Or Master of Science in Computer, Electrical Engineering or similar
    • 3+ years experience in ASIC digital design domain
    • Team oriented person with clear verbal and written communication
    • Exposure to CPU/processor architectures; RISC-V experience highly desirable
    • Knowledge of design techniques for high performance and low power
    • Must have strong digital design fundamentals
    • Hands-on expertise with Verilog, System Verilog
    • Hands-on expertise with debugging failed scenarios using DVE/Verdi
    • Hands-on expertise with Spyglass, Design Compiler, TCM/Fishtail
    • Experience in developing scripts using Perl, Python, Javascript or similar languages
    • Hands-on expertise debugging CPU designs is highly desirable
    • Excellent debug and problem solving skills
    • Experience with git or other revision control environments
    • Exposure to automotive safety (ASIL) standards is an advantage
    The base salary range across the U.S. for this role is between $122,000-$182,000 a year. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

    Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

    Job Category

    Engineering

    Country

    United States

    Job Subcategory

    ASIC Digital Design

    Hire Type

    Employee

    Base Salary Range

    $122,000-$188,000

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