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    Memory Design Engineer - Santa Clara, United States - OVT group

    OVT group
    OVT group Santa Clara, United States

    1 week ago

    Default job background
    Description


    We are looking for qualified Memory circuit design engineers who have a good understanding of analog circuit and CMOS Image Sensor.

    Responsibilities -


    Work on detailed transistor level design of analog and mixed signal circuits in memory (DRAM/SRAM) for display chip or image sensor.

    Perform the whole chip simulation along with the block level, transistor level schematic simulations.
    Perform the block level and transistor level layout design using CAD tools like Cadence Virtuoso and Calibre.
    Collaborate with verification, process, test, and application engineers to debug, characterize and optimize the performance.
    Requirements -

    Experience/knowledge in SRAM/DRAM.
    MSEE or equivalent
    Must have 2+ yrs of relevant experience.
    Experience/knowledge in display chip or image sensor and camera system is a plus
    Annual base salary for this role in California, US is expected to be between $110,000 - $130,000.

    Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

    EOE/Minorities/Females/Vet/Disability
    #J-18808-Ljbffr


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