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    Wafer Level Packaging Research Integration Engineer - Boise, United States - Idaho State Job Bank

    Idaho State Job Bank
    Idaho State Job Bank Boise, United States

    2 weeks ago

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    Description


    Wafer Level Packaging Research Integration Engineer at Intel in Boise, Idaho, United States Job Description Job Description Drives design, simulation, development, and implementation activities for scientific research projects leveraging device physics and electromagnetics theory, thermomechanical analysis and simulations, materials, chemistry, and process innovations to drive research on novel devices, packages, interconnects, circuits, and systems.

    Investigates the feasibility of applying scientific principles and concepts to potential inventions and products years before landing on a product roadmap.

    Develops prototypes to demonstrate proof of concepts.

    Designs, fabricates, and performs etest assessment of novel devices, packages, and interconnects including DC testing, RF smallsignal and largesignal characterization techniques, pulsing, and stressing.

    Establishes etest methodologies, metrics, and criteria of a device based on required application specifications.

    Provides process solutions across different production modules including lithography, etch, diffusion, CVD, PVD, CMP, and overall systems requirements, including thermomechanical, power delivery and highspeed signaling, and cost.

    Owns critical process and equipment research that enable rapid device miniaturization and the mass production of integrated circuits.

    Quantifies the tradeoffs between various device, circuit, and system parameters, generating and exploring novel solutions to meet and solve the demands for continued performance improvements in devices, packaging, and systems.

    Develops innovative solutions to enable Intel's roadmap of future assembly packaging platform technologies.

    Uses handson approach to plan, setup, and execute experiments in collaboration with device, module, reliability, analytical labs, and TCAD across fabrication sites and quantifies and benchmarks experimental results with best known methods and literature/academia.

    Develops and validates models and the necessary measurements to advance the understanding of device physics, packaging, and systems. Leads and manages vendor engagements to support various research and development activities across devices, packages, and interconnects. Mentors external research in academia and industry consortia to help fill Intel's internal research pipeline. Qualifications For information on Intel's immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information (. You must possess the below requirements to be initially considered f To view full details and how to apply, please login or create a Job Seeker account
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