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    pll circuit design engineer - Santa Clara, United States - Tekwissen

    Tekwissen
    Tekwissen Santa Clara, United States

    3 weeks ago

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    Description

    Job Title:

    PLL CIRCUIT DESIGN ENGINEER

    Work Location:
    Santa Clara CA 95054

    Duration: 6 Months


    Work Type:
    Contract


    Job Type:
    Onsite


    Pay Rate:
    $50-53/Hourly/W2


    Overview:
    TekWissen Group is a workforce management provider throughout the USA and many other countries in the world.

    This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets.

    global company that specializes in manufacturing semiconductor devices used in computer processing.

    The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.


    Job Description:


    Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.

    Solid knowledge of industry standard tools and practices for analog circuit design
    Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
    Quality-oriented mindset
    Strong and effective communication skills and team spirit


    KEY RESPONSIBILITIES:
    Help design of building blocks of a PLL
    Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
    Work closely with layout engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution


    PREFERRED EXPERIENCE:
    3-5 years of professional experience in the semiconductor industry
    Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm

    Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.

    Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.

    Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.

    Helic/EMX is a plus.
    Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
    Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
    Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
    Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
    Possess strong analytical/problem solving skills and pronounced attention to details
    Must be a self-starter, and able to independently drive tasks to completion


    ACADEMIC CREDENTIALS:
    Master's in electrical engineering or equivalent preferred

    TekWissen Group is an equal opportunity employer supporting workforce diversity.

    #J-18808-Ljbffr
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