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    RTL Design Engineer - Santa Clara, United States - ObjectWin Technology

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    Description

    RTL Design Engineer - Specialized (US)

    Location:

    San Jose, CA 95124 Onsite


    12 Months Contract

    Job Description:

    Location:
    Onsite San Jose, CA


    JOB DUTIES:

    Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.


    EDUCATION:
    Bachelor's or Master's in Computer Engineering


    KEY RESPONSIBILITIES:


    • Perform RTL design of digital components in Verilog/systemverilog.
    • Analyze/fix Lint and CDC errors of the components.
    • Guarantee quality/timely deliverables meeting project's schedule.
    • Help to improve/automate design process.

    PREFERRED EXPERIENCE:


    • Knowledge of
      RISK-V processor integration Express

    • Multi-clock domain designs.
    • Design constraints for
      synthesis and static timing analysis.
    • Knowledge of
      AXI/AMBA protocol
    • Knowledge of
      front-end RTL design tools and methodologies.
    • Knowledge of
      scripting languages like Perl, tcl or cshell


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