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    Design Engineering Intern - Austin, United States - Cadence Design Systems

    Cadence Design Systems
    Cadence Design Systems Austin, United States

    2 weeks ago

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    Description

    At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

    The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Silicon Solutions.

    Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin . This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.Come be part of this great SSG Team where you can make an impact that is visible. Design Engineering Intern positions are for one of two roles:(a) Perform as a member of the Logic Design Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for the RTL implementation of high performance memory system and interconnect components. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.(b) Perform as a member of the Design Verification Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for verification of high performance memory system and interconnect components. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

    Position Requirements: Currently enrolled as MS/BS in Electrical Engineering, Computer Engineering, or a similar major. Deep understanding of Digital Design and/or Design Verification Fundamentals Excellent automation skills using Tcl, Perl, shell scripting Excellent oral and written communications skills Exposure to design automation tools is a plus

    Were doing work that matters. Help us solve what others cant.

    Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

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