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    RM - Physical Design Engineer - Phoenix, United States - Energy Jobline CVL

    Energy Jobline CVL
    Energy Jobline CVL Phoenix, United States

    4 weeks ago

    Default job background
    Description
    Duration:0-8 month(s)


    Description/Comment:
    LEVEL 9

    CM&T

    Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms.

    Work across the entire silicon design lifecycle, including system architecture, design verification, RTL digital design, physical design, design for test (DFT), and Emulation.

    " What type of education is needed for this position? BS in Computer Science or Electrical Engineering

    " Work location :
    Phoenix, AZ

    " Will this role work remote/In Office/Hybrid (in office & remote) Remote is a possibility.

    " Does this role require vaccination mandate? Yes

    " Does the resource have to be Local:

    " Does this role have any *Visa Restrictions (see red info below)? US

    or Green Card Holder

    " Will the client pay for travel and expenses? Yes, with prior approval

    " Is industry experience needed for this role and why? Yes, 3-7 years

    experience in semiconductor design and development.

    "

    must-have

    skills for this role


    • Electrical Engineering
    • Electronic Design Automation (EDA)
    • Semiconductor Design & Development
    " Years of experience required for each skill? 3-7 years

    experience

    "

    nice-to-have


    skills :

    • Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs
    • Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors
    • Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design
    " What are the chances for extension? 100%, purely based on performance.

    " The Work:

    " Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis, power analysis, IR Drop, EM, in advanced technology nodes

    " Resolve power issues related to physical design, identify potential low power solutions, drive execution and methodology improvements

    " Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design

    Here s what you need:
    " A minimum of three years of experience with:

    o RTL2GDSllon advanced technology nodes (7nm and below)

    o Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.

    o Power constraints

    and validation, power analysis, interface with power integrity analysis tools.

    o TCL, Python and/or Perl programming

    o EDA tools like DesignCompiler/Genus, Primetime/PrimePower, ICC2/Innovus, Redhawk/Voltus

    " Bachelor s Degree or equivalent (12 years) work experience (If an, Associate s Degree with 6 years of work experience)


    Bonus points if:
    " Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs

    " Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors

    " Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design

    Additional
    Job Details:
    • Electronic Design Automation (EDA) (P
    • Advanced) |
    • Semiconductor Design and Development (P
    • Advanced)
    #J-18808-Ljbffr
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