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    Product Engineer - San Francisco, CA, United States - SQL Pager LLC

    SQL Pager LLC
    SQL Pager LLC San Francisco, CA, United States

    2 weeks ago

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    Description
    Principal/Senior Staff/Staff GPGPU Design Engineer
    Client Overview Client is building the first latency optimized SoC for their industry.

    Using its proven AI accelerator designs, it is targeting best in class latency with order of magnitude improvements for years to come.

    Low Latency has become the key enabler for the niche and other real-time application and the current industry' state-of-the art is just not up to the task.

    Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field.

    We are now building the corresponding SoC, to deliver unrivaled products to mission-critical and real-time applications.

    This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellency.

    You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve our products' performance, quality and cost.

    We are seeking a dedicated hands-on GPGPU Design Engineer to help develop an GPGPU for our artificial intelligence computing architecture


    • As a Design Engineer, you will be participating in Architecture definition and modeling, verification test plan and testbench architecture.
    • You will be responsible for developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.
    • Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoC.
    • Define a micro-architecture for the implementation and the usage of the functional block IP, possibly with external sourced IPs.
    • Work with the Physical design team for the timing closure

    10+years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of general experience as an GPGPU Digital Design Engineer.


    • Expert in RTL Logic Design, CDC, RDC, Scan insertion, Lint, LEC., Experience in low-power design with UPF.
    • Scripting experience with Tcl, Python (or similar) language.
    At least gone through entire ASIC design phases; Neural Network Computation Flow on GPU/NPU


    • SIMD/SIMT Processing Pipelines
    • GPU cache hierarch and Latency-hiding with NoC Inter-connect bus fabric
    Knowledge in various DNN networks and their core ASIC implementations
    Knowledge of OS, software/hardware interface
    Finite Precision Analysis of multi-layer compute processing pipeline
    Medical insurance
    ~ Dental insurance
    ~
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