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    Circuit Design Engineer - Santa Clara, United States - Managed Staffing

    Managed Staffing
    Managed Staffing Santa Clara, United States

    3 hours ago

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    Description

    PLL CIRCUIT DESIGN ENGINEER
    Remote candidates are acceptable as long as they are in the US.

    The Role


    We are searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering products.

    Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area Looking forward to welcoming you in the team

    The Person


    Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.

    Solid knowledge of industry standard tools and practices for analog circuit design

    Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python

    Quality-oriented mindset

    Strong and effective communication skills and team spirit

    Key Responsibilities

    Design of building blocks of a PLL including architecture development and transistor level circuit design

    Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.

    Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

    Preferred Experience

    5-8 years of professional experience in the semiconductor industry

    Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm


    Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.


    Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.


    Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.

    Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.

    Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)

    Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.

    Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy High-frequency design experience

    Possess strong analytical/problem solving skills and pronounced attention to details

    Must be a self-starter, and able to independently drive tasks to completion

    Academic Credentials

    Master's in electrical engineering or equivalent preferred
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