- Innovate on 3DIC Heterogenous integration as a holistic cooptimization from System to Silicon in partnership with domain experts, extending DTCO to STCO (System Technology Co-Optimization).
- Establish 3DIC prototypes across market segments. Collaboration with Product teams to identify critical product characteristics and target setting requirements.
- Engage with EDA providers on pathfinding of 3DIC EDA feature requirements and 3DIC design methodology.
- Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation
- Design analysis and optimization for 3DIC Advanced Silicon and Packaging technology definition and certification.
- 3DIC Test Chips validation of 3DIC technology platforms and design methodology
- Expert on establishing Static Timing Analysis (STA) methodology and signoff including variation analysis.
- Experience driving digital design flows and EDA vendor engagement.
- Experience with Testchip designs and/or Product designs.
- Multiple clock domain and Low Power Design.
- Scripting skills using a programming language such as Python, TCL
- Physical Design Methodologies for optimal Performance Power Area Cost (PPAC) in advanced technologies.
- Experience with ARMbased system PPA optimization
- Reference designs and TFM for STCO/3DIC.
- Circuit design, Standard Cell Library and Memory Architectures.
- Power Management Design Methodology and Power Distribution Network (PDN), IR/EM, Thermals.
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Senior 3D-IC Design Methodology Engineer - Oregon, United States - Intel
Description
Job DescriptionThe Group:
Intel's Advanced Design (AD) team resides within the Design Enablement (DE) organization, which collaborates closely with our partners in process technology, IP, and products spanning client/server and networking products.
The primary focus of AD is to guide process technology definition, and design prototypes in Intel's latest process technology, supporting Intel's internal and external design customers.
The future of Moore's Law: 3D-IC :The Role:
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization).
Your responsibilities may include, but not be limited to:
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a MS degree with 4+ years of experience or PhD degree with 2+ years of experience in Electrical Engineering or Computer Engineering and or related field.
Preferred Qualifications:
4+ years of experience in the following:
Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations US, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.Find more information about all of our Amazing Benefits
here.
Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
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