Head of Design Verification, Interface IP - San Jose

We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. · 10 years of design verification experience with ownership of complex IP or SoC subsystemsDeep hands-on expertise in SystemVerilo ...

We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. · ...

++We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. · + ...

We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. · You will lead Interface IP DV from architecture definition through tape-out, · working closely with RTL designers, IP vendors, S ...

We're building the next generation of full-system emulation and verification solutions—and we're looking for a seasoned Design Engineer to help lead the way.You will work hands-on with Palladium and Protium emulation platforms developing high-fidelity models and end-to-end verifi ...

+We're building the next generation of full system emulation and verification solutions—and we're looking for a seasoned Design Engineer to help lead the way. · You'll work hands-on with Palladium and Protium emulation platforms, developing high-fidelity models and end-to-end ver ...

· Core Responsibilities: · As a DDR Applications Engineer you will be involved with customer interfacing on all phases of phy and controller design of high performance ddr interface from RFQ, RTL to delivery of our final GDSII. Your responsibilities include but are not limited t ...

· Principal Engineer, ASIC Design Verification  · Location:  San Jose (on-site) · Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, an ...

Prodapt is seeking a highly skilled and adaptable engineer to join our dynamic team, focusing on System-on-Chip (SoC) verification. · ...

Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. · ...

The company is hiring an ASIC/SoC Design Verification Engineer in San Jose. The ideal candidate has MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree. · In depth knowled ...

Requirements: MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree. In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware ...

Responsibilities · Own verification of entire FPGA design used in high-end router products · Understand design specifications and interact with design engineers to identify verification scenarios · Create test plans, constrained-random verification environments, test cases, regre ...

We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead driving high-quality silicon from concept to tape-out. · Architect Testbenches: Define and bui ...

We are seeking a highly · experienced Senior Principal Engineer to lead the verification of cutting-edge data center and networking silicon solutions.We are looking for someone with deep technical expertise in PCIe protocols host interfaces and complex SoC subsystems Strong prof ...

· .Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Conn ...

The position of FPGA Verification Engineer involves owning the verification of entire FPGA design used in high-end router products. · ...

Dice is seeking Design Verification Engineers with 6-15+ years of experience. Apply via Dice today. · Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. · Develop test plans ...

We are looking for a Field-Programmable Gate Arrays (FPGA) engineer to work on the verification of FPGA designs used in high-end router products. · Owning verification of entire FPGA design used in high-end router products. · Understanding design specifications and interacting w ...

The FPGA Verification Engineer will own verification of entire FPGA design used in high-end router products. · Create test plans, · constrained-random verification environments, ...