Principal Engineer, ASIC Design Verification - San Jose, CA

Only for registered members San Jose, CA, United States

1 month ago

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Job summary

We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead driving high-quality silicon from concept to tape-out.

Responsibilities

  • Architect Testbenches: Define and build modular reusable and scalable UVM testbench architectures for complex IP blocks and Sub-systems.

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