Formal Verification Engineer (PhD Intern 2026) - San Jose, CA
5 days ago
Job summary
You will be responsible for formal verification of high-performance design IPs/interconnects and memory subsystems that form the backbone of cloud and hyperscaler computing platforms.Responsibilities
* Develop detailed FV test plans based on design specifications* Identify critical IP logic and key micro-architectural properties that guarantee design correctness* Code and implement FV abstractions, models, assertions,and perform assertion model checking to uncover corner-case bugs*
,- Implement FV complexity reduction techniques using EDA/academic FV tools to achieve proof convergence or sufficient proof depth. ,
- Develop and code scripts to improve FV productivity and efficiency. ,
- Assist designers in implementing assertions and FV testbenches for unit/block-level RTL. ,
- Aparticipar en revisiones de diseño y trabajar estrechamente con equipos de diseño para mejorar interfaces de diseño e integridad del diseño (PPA) según la retroalimentación del análisis formal de arquitecturas micro.
Job description
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