SOC Verification Engineers - San Jose, CA

Join Broadcom's custom silicon division as a Verification Engineer. Work on IPs for ASIC products like custom AI chips. · ...

We are looking to grow our team with an Mixed-Signal Verification Engineer.This person will help develop and implement mixed-signal verification and IC designs based on team architecture and specifications. · ...

We are looking for a Mixed-Signal Verification Engineer to help develop and implement mixed-signal verification and IC designs based on team architecture and specifications. · * Experience in Spice Simulation* Systems Verilog modeling experience* Strong understanding of both anal ...

We are looking to grow our team with an Mixed-Signal Verification Engineer. · Experience in Systems Verilog. · Working with HDL and ADC / DAC. · ...

We are looking to grow our team with an Mixed-Signal Verification Engineer This person will help develop and implement mixed-signal verification and IC designs based on team architecture and specifications.The ideal candidate will have experience in Systems Verilog and well as in ...

Develop and enhance UVM-based testbenches to verify complex designs. · ...

We are looking for Verification Engineers to collaborate with our team. You will drive pre-silicon RTL verification of the full chip and stay abreast with design specs. · We're looking for candidates who are well-rounded in all aspects of verification. · ...

Develop and enhance UVM-based testbenches to verify or accelerate the simulation of complex designs at component or subsystem level. · ...

Altera is seeking a Senior Design Verification Engineer to drive verification of complex FPGA and SoC designs from architecture through silicon validation. · ...

Altera is seeking a Senior Design Verification Engineer to drive verification of complex FPGA and SoC designs from architecture through silicon validation. · ...

We are seeking a Design Verification Engineer to ensure the quality at the heart of our GPU architecture. · Work with architects and designers to build verification environments and test plans. · Craft functional verification coverage strategy to ensure complete test suite implem ...

Dice is seeking Design Verification Engineers with 6-15+ years of experience. Apply via Dice today. · Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. · Develop test plans ...

The FPGA Verification Engineer will own the verification of entire FPGA design used in high-end router products. · ...

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, · End to end ownership of one or more ...

This role offers a great opportunity to be at the forefront of compiler verification, ensuring our brand-new technology maintains its premier standard. · Design industry grade C++ testsuite · Identify potential gaps in current test procedures · ...

+Job Summary · +As a verification engineer with a knowledge of subsystems and SoCs, · +you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. · Writing test plans · ...

We are looking for humble geniuses who believe that engineering has the potential to make the impossible possible. · ...

The FPGA Verification Engineer will own verification of entire FPGA design used in high-end router products. · Create test plans, · constrained-random verification environments, ...

We are seeking a highly skilled GPU Design Verification Engineer to join our team. · Developing and executing verification plansCreate testbenchesDebugging complex GPU designs ...

The position of FPGA Verification Engineer involves owning the verification of entire FPGA design used in high-end router products. · ...

Responsible for ASIC design verification for various processing blocks within a SOC. · Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments. · Design and implement constrained-random and directed System Verilog testbench ...