- Use industry standard tools to implement scan in complex IP, and generate high coverage ATPG patterns utilizing scan compression and verification.
- Analyze scan coverage, and implementation issues and develop strategies to address quality and efficiency.
- Build a verification environment to run and debug gate-level simulations.
- Document scan designs and maintain guidelines for best scan design practices.
- Define, develop, and improve scan design process flows and methodologies for continuous improvement.
- Run, debug, and perform diagnostics on scan patterns post-silicon on a production and debug tester.
- Assist MBIST/DFT leads and Interact with RTL counterparts to resolve design issues.
- Running MBIST simulations, including gate-level with timing corners and debugging.
- MSEE or BSEE with 5+ years relevant experience preferred (or equivalent education and experience).
- Hands-on responsibility from MBIST insertion to verifications.
- Have 2+ years of experience with Synopsys ATPG TetraMAX or Mentor Fastscan.
- Knowledge of low-power design methodologies.
- Must have scripting and automation skills – Preferred Python and Perl, TCL.
- Experience with synthesis, static timing analysis, and ATPG modeling.
- Knowledge of stuck-at, transition, IDDQ, and other advanced fault models.
- Strong working knowledge of VCS RTL/GLS simulations and debugging.
- Experience in Tessent MBIST flows and tools.
- Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python are preferred.
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DFT/MBIST Engineer - Sealy, United States - Zenex Partners
Description
DFT/MBIST Engineer
Location:- Austin, TX
Duration:- 9 Months
Pay rate:- $75 - $100/hr W2.
Check all associated application documentation thoroughly before clicking on the apply button at the bottom of this description.
Responsibilities of DFT/MBIST Engineer
Requirements for DFT/MBIST Engineer