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PHY Design Engineer/Lead - California, United States - InnoPhase IoT
Description
PHY Design Engineer/LeadJob Description:
Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT/BLE micro-architecture and design.
You will be involved in the design development cycle, which includes participating in high-level product specifications, RTL development, working closely with Algorithm and verification engineers.
Your specific responsibilities may include but are not limited to the following:Develop and refine Digital Signal Processing engines for wireless communication systems.
Develop micro-architecture, and SystemVerilog RTL to meet size, timing, and power target.
Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, and optimizations.
Develop, and refine design, verification and analysis tools and flows, as needed.
Work closely with Verification, and Validation teams on test-plans, coverage-analysis
Work closely with Physical Design teams to provide guidance on Floor planning, specification of constraints, and timing closure.
Required Qualifications:
BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
12+ years of experience in RTL design using Verilog, SystemVerilog
Understanding of Digital Signal Processing theory, and mapping to design
Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies
Ability to work independently, and proactively identify and resolve issues.
Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs
Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
Enjoy debugging, and problem solving in a team environment.
Preferred Qualifications:
Experience in Low Power design development, involving multiple power, and voltage domains.
Embedded SW & HW design is a strong plus.
Experience with Python, Perl, Tcl, C/C++ and shell scripts.
Experience with lab debug, multi-team, multi-site working environment is a strong plus.
Experience with ASIC and FPGA synthesis flows utilizing industry leading flows.
Experience using PowerArtist/Joules and providing actionable feedback into design.
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