Lead Design Verification Engineer - Redmond

FPGA verification engineer needed with strong expertise in SystemVerilog and UVM methodology for IP/Module-level verification. · Lead and execute IP / Module-level Design Verification using SystemVerilog and UVM · Architect, develop, and maintain UVM testbenches from scratch (not ...

We're leveraging our experience in building rockets and spacecraft to deploy Starlink, · a world's most advanced broadband internet system. · We design, build, test, · and operate all parts of the system – thousands of satellites, · consumer receivers that allow users to connect ...

SpaceX is actively developing technologies to make humanity's future in space possible. · We design, build, test, and operate all parts of the Starlink system – thousands of satellites, · consumer receivers that allow users to connect within minutes of unboxing, · and the softwar ...

We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, · and new ways to map the human body.We believe the only way to achieve our goals is to look a ...

SpaceX is seeking a motivated and proactive engineer to work alongside world-class cross-disciplinary teams on developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures. · Responsible for digital ASIC verification at block and system level · ...

We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, · sensors and new ways to map the human body. · Define and implement verification plans · Develop funct ...

We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics displays sensors and new ways to map the human body Our chips will enable Meta's Wearable devices that blend our r ...

+Be part of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. · Implement a state of the art verification environment to facilitate testing of the RTL against reference ...

+We are seeking a skilled and detail-oriented Electrical Test Engineer to join our HW engineering team for the future of AR/VR products.+ · +Design and execute the EE validation and performance characterization of test systems throughout a program life cycle. · Work closely with ...

Design verification expertise in System Verilog/UVM for unit/module level verification. · Lead design verification team with a minimum of 5 members. · ...

Expertise in System Verilog/UVM for Unit/Module level Verification. · ...

We are seeking an experienced Lead Design Verification Engineer with strong hands‑on expertise in SystemVerilog and UVM.The ideal candidate will have prior experience leading a Design Verification team as well as contributing individually at a technical level. · This role require ...

Become an integral part of a team focused on design verification for complex IPs and subsystems within modern FPGAs. · ...

Microsoft is looking for a Design Verification Engineer to join the team behind its expanding Cloud Infrastructure and responsible for powering Microsoft's 'Intelligent Cloud' mission. · ...

· A SpaceX estamos desarrollando tecnologías para hacer posible la vida humana en Marte. · Necesitamos ingenieros experimentados para ayudar a maximizar el potencial del sistema Starlink en todo el mundo. · Diseño de ASICs de próxima generación. · Cierre de cobertura funcional. ...

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink the world's most advanced broadband internet system. We design build test and operate all parts of the system thousands of satellites consumer receivers that allow users to connect wit ...

Design verification expertise in system verilog/uvm for unit/module level verification; strong background in developing uvm testbenches from scratch; experience in vip integration and bring up; porting existing verilog/vhdl environment to uvm based environment. · He should have s ...

We are looking for a Senior Design Verification Engineer to join Microsoft's Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team.This is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" missio ...

We are seeking a motivated engineer who will work alongside world-class cross-disciplinary teams to develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. · Responsible for digital ASIC and/or FPGA verification at block and ...

We are looking for a Principal Design Verification Engineer to join the AI Silicon Engineering (AISiE) SoC Design Verification team. The successful candidate will have experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or sys ...

The Validation Team mandate is to ensure hardware and product requirements are met across our device portfolio. · As a Design Verification Engineer, you will require working closely with a wide range of cross functional partners. Some of those partners include the product design ...