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    Senior Verification Engineer - Austin, United States - Microsoft

    Microsoft
    Microsoft Austin, United States

    1 week ago

    Microsoft background
    Full time
    Description

    Overview

    Microsoft Azure is building the fastest network in public cloud. We are seeking candidates who can span the stack from hardware to systems to applications, turning ideas into production systems at a rapid pace. Join us as a Senior Verification Engineer to build the world's fastest public cloud and make a difference to millions of people across the planet.

    As a Senior Verification Engineer in the Accelnet Hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array (FPGA) SmartNICs (Azure Boost) in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, improving network security, enhancing connection establishment performance, and improving performance with Remote Direct Memory Access (RDMA) and custom network protocols. You should be able to drive projects with both hardware and software teams, both inside and outside of Microsoft.

    This is a unique opportunity for a Senior Verification Engineer to see Register-Transfer Level (RTL) code go to production within weeks instead of years. Come help build one of the few truly hyperscale global clouds with innovations possible at every level of the computing stack.

    Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

    Qualifications

    Required Qualifications:

  • 7+ years of technical engineering experience in hardware design verification, verification methodologies, and system VerilogOR Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field AND 5+ years of technical engineering experienceOR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field AND 3+ years of technical engineering experienceOR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field.
  • 3+ years of technical engineering experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals.

    • Other Qualifications:

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

    • Preferred Qualifications:

  • 10+ years of technical engineering experienceOR Bachelor's degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years of technical engineering experience with hardware design verification, verification methodologies, and system VerilogOR Master's degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 6+ years of technical engineering experience with hardware design verification, verification methodologies, and system VerilogOR Doctorate degree in Electrical Engineering, Computer Engineering, Mechanical Engineering,or related field AND 3+ years of technical engineering experience with hardware design verification, verification methodologies, and system Verilog
  • Understanding of constrained random verification principles and experience in writing comprehensive test plans,AND system Verilog constraints, functional coverage, and assertions,AND networking fundamentals, including protocols such as IPV4, IPV6, TCP, UDP, DTLS, among others,AND formal verification
  • 10+ years of project experience verifying several designs at unit and system level.
  • Experience in scripting languages such as Python and PowerShell.

    • Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

    Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

    Microsoft will accept applications for the role until April 25, 2024.

    Responsibilities

  • Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies.
  • Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams.
  • Execute the test plan by adding testcases and :957 tracking verification through coverage driven metrices.
  • Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage.
  • Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow.
  • Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features.
  • Handle occasional on-call responsibilities for addressing hardware issues reported by our customers.

    • Embody ourand

    Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Industry leading healthcareEducational resourcesDiscounts on products and servicesSavings and investmentsMaternity and paternity leaveGenerous time awayGiving programsOpportunities to network and connect
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