Post -Silicon Engineer - DDR Memory - Sunnyvale, United States - Cays Inc

Customer-Focused Silicon Validation Engineer- DDR/Memory Tuning

3 weeks ago

The Role: · Ampere Computing is seeking a Customer-Focused Post-Silicon Validation Engineer- DDR / Memory Tuning to join a talented and experienced team to validate server class products for memory sub-system that power Cloud, Enterprise, and Data Center Ampere's competitive edg ...

Customer-Focused Silicon Validation Engineer- DDR/Memory Tuning

1 week ago

· The Role: · Ampere Computing is seeking a Customer-Focused Post-Silicon Validation Engineer- DDR / Memory Tuning to join a talented and experienced team to validate server class products for memory sub-system that power Cloud, Enterprise, and Data Center Ampere's competitive ...

Customer-Focused Silicon Validation Engineer- DDR/Memory Tuning

3 weeks ago

· The Role: · Ampere Computing is seeking a Customer-Focused Post-Silicon Validation Engineer- DDR / Memory Tuning to join a talented and experienced team to validate server class products for memory sub-system that power Cloud, Enterprise, and Data Center Ampere's competitive ...

Customer-Focused Silicon Validation Engineer- DDR/Memory Tuning

3 hours ago

Description · The Role: · Ampere Computing is seeking a Customer-Focused Post-Silicon Validation Engineer- DDR / Memory Tuning to join a talented and experienced team to validate server class products for memory sub-system that power Cloud, Enterprise, and Data Center Ampere's ...

Post -Silicon Engineer

2 weeks ago

Job Description: · HBM / DDR expert · Experience in memory validation · Understanding of memory training and understanding of memory test algorithms · Skills : Python,C/C++, experience with bare metal and Linux OS, embedded SW development, Git/Perforce · 10+ years' experience · ...

Architect

1 week ago

Job Description: · We are looking for a solid technical individual contributor to help undertake existing and some next generation DDR/HBM memory interface PHY IP development. The candidate should have expertise in source synchronous systems, considerable practical experience wi ...

Architect

1 week ago

Job Description: · We are looking for a solid technical individual contributor to help undertake existing and some next generation DDR/HBM memory interface PHY IP development. The candidate should have expertise in source synchronous systems, considerable practical experience wit ...

Verification Engineer

3 weeks ago

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabiliti ...

Verification Leader

3 weeks ago

Our Silicon IP business is all about integrating more capabilities into an SoCfaster. We offer the worlds broadest portfolio of silicon IPpredesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. ...

sr. design verification engineer

4 days ago

Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet solu ...

sr. design verification engineer

3 weeks ago

· Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet s ...

sr. design verification engineer

3 weeks ago

Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet solu ...

SoC/IP Technical Lead

2 weeks ago

Job Description and Requirements · Are you interested in working across various market segments (AI, Cloud, Networking, Storage...), designs, foundries and processes ranging from 5nm (and below) to 28nm (and above) to develop solutions for customer's chip designs using the Synop ...

Applications Engineering, Principal Engineer

1 week ago

SoC/IP Technical Lead · 47894BR · USA - California - Mountain View/Sunnyvale, USA - California - San Jose · Job Description and Requirements · Are you interested in working across various market segments (AI, Cloud, Networking, Storage...), designs, foundries and processes ran ...

Tech Lead Firmware Engineer

1 week ago

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture tha ...

Memory Subsystem Architect

6 days ago

Requirements · • Knowledge in one or more of the following areas, memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory. · • Knowledge and experience with common performance benchmarks and workloads. · • Knowledge in fabric interconnect protocols such as ARM AXI and ...

Electrical Validation

1 week ago

Responsibilities:Experience in Post Silicon Electrical Validation of server processors (if server processor is too specific, you can remove server) · High speed communication principles, circuits and signal integrity principles · Computer architecture knowledge · DRAM architectur ...

Memory Subsystem Architect

4 days ago

Requirements · Knowledge in one or more of the following areas, memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory. · Knowledge and experience with common performance benchmarks and workloads. · Knowledge in fabric interconnect protocols such as ARM AXI and CHI. ...

Memory Subsystem Architect

3 days ago

Requirements · • Knowledge in one or more of the following areas, memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory. · • Knowledge and experience with common performance benchmarks and workloads. · • Knowledge in fabric interconnect protocols such as ARM AXI and ...

Senior Firmware Engineer

3 hours ago

We are now looking for a Senior Firmware Engineer for our Memory Subsystem Team · Widely considered to be one of the technology world's most desirable employers, NVIDIA is an industry leader with groundbreaking developments in High-Performance Computing, Artificial Intelligence a ...