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PHY Verification Engineer/Lead - California, United States - InnoPhase IoT
Description
Job Description:
Join Innophase IoT group as a hands-on PHY Verification Engineer/Lead and be responsible for Low-power WiFi, BT/BLE verification.
You will be involved in the design development cycle, which includes participating in high-level product specifications, UVM Testbench design, test planning, working closely with Systems, SW, and design engineers.
Your specific responsibilities may include but are not limited to the following:Define, Develop, and refine hierarchical UVM testbench for verification of wireless PHY and MAC layers.
Work closely with design and system engineers to develop constraint random testbench with reference C model.
Identify bottlenecks in design and verification coverage and provide feedback on potential optimizations.
Work closely with Verification, and Validation teams on test-plans, coverage-analysis
Maintain releases, run, and track regressions, and identify functional and code coverage gaps.
Develop, and refine design, verification and analysis tools and flows, as needed.
Required Qualifications:
BSEE or MSEE, with experience in UVM testbench development, constraint random testing, coverage analysis.
12+ years of experience in RTL, and gate-level verification
Basic understanding of Digital Signal Processing theory
Experience in verifying WiFi Physical Layer, and/or another Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies.
Experience with Incisive/Xcelium/VCS, Verdi or equivalent tools
Enjoy debugging, and problem solving in a team environment.
Preferred Qualifications:
Experience in verifying Low Power designs, involving multiple power, and voltage domains.
Establish System Verilog Assertions for functional verification.
Embedded SW & HW design is a strong plus.
Experience with Python, Perl, Tcl, C/C++ and shell scripts.
Experience with lab debug, multi-team, multi-site working environment is a strong plus.
Experience with ASIC and FPGA synthesis flows utilizing industry leading flows.
Experience using PowerArtist/Joules and providing actionable feedback into design
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