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    Design Verification Engineer - Atlanta, United States - Montage Technology Inc

    Montage Technology Inc
    Montage Technology Inc Atlanta, United States

    3 weeks ago

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    Description

    About Us:
    Montage Technologies has opened a new U.S. location in the Johns Creek, Atlanta Georgia area. We are a leading semiconductor company specializing in enterprise-class memory interface products.


    Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets.

    Montage provides industry leading memory interface products for the demanding cloud computing and data center markets.

    Our robust product portfolio includes the critical components required by the memory modules, such as Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC).

    Compliant with JEDEC specifications, these products are designed for a variety of memory modules, to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.


    Job Description:


    We are looking for Verification Engineers who will help develop system level UVM test benches for various DDR5 DIMM products, Power Management IC (PMIC) and also CXL 2.0 products.

    Your contribution would be to lead and work with other global team members in building the infrastructure for system level SoC testing.

    You will also be responsible to functionally verify the system and IP components, using SystemVerilog and mixed signal verification techniques.


    Key Responsibilities:
    Be knowledgeable in DDR5 DIMM system level verification and PMIC IP verification
    Collaborate closely with component testing verification teams across our global sites
    Interface with other engineering functions such as Design, Product, Spec Engineering
    Be involved in silicon debug when necessary
    Develop, drive and implement UVM SystemVerilog Testbench and infrastructure
    Develop stimulus, coverage, SV assertions, scripts as necessary.
    Provide mentorship to junior engineers
    Debug regressions and failing simulations


    Job Qualifications:
    BS or MS in Electrical Engineering, Computer Engineering or equivalent
    5+ years of relevant work experience
    Good understanding of CMOS circuit design
    Strong understanding and hands-on experience in building UVM Testbenches from scratch
    Proficient with digital and analog simulation tools, e

    g:
    VCS, Xcellieum, Verdi etc
    Excellent debugging and problem-solving skills
    Strong understanding of DDR5 protocol or CXL 2.0 spec


    Montage offers a competitive compensation package including base salary, bonus, equity, matching 401(k), comprehensive medical and dental benefits, and a time-off program.

    For more information about Montage, please visit our website at montage-

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