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RTL Design Engineer CPU - Stanford, United States - VMware
Description
**RTL Design Engineer CPU & Server Platform**
CAROUSEL_PARAGRAPH
No
Palo Alto, California
Software Engineering
R
** Share Job**
mail_outlineGet future jobs matching this search
or ** Job Description**
**Business overview:**
We are CPU & Server Platform team responsible for ESXi operating system and core virtualization infrastructure. In this role you will be part of Hardware team creating next generation HW accelerators that significantly influence Data center virtualization. You would join a cross-discipline team of highly capable and motivated engineers, designers and validators. You will have the opportunity to transform your ideas into World-changing technologies & Products for Datacenter growth . Work with Research Groups, Platform Engineering teams at all layers of Hardware & Software - from FPGA BS to Firmware to OS (ESXi) to Hypervisors. You will have the opportunity to influence external FPGA , Silicon & platform vendors and VMW partners.
**What will I be responsible for**
Responsible for Macro & Microarchitecture of the overall FPGA chip and the design, verification, debug of individual IP blocks
Development and refinement of RTL design to target power, performance and timing goals
Own Microarchitecture development and specification from high-level arch exploration, through micro architectural research towards a detailed specification
Provide support to HW validation to run simulations, work with S/W and other team members to predict and validate performance results
Work with multi-functional engineering teams to implement physical design and delivery
Lead collaborative technical discussions to drive resolution on issues with internal teams and external HW partners
Develop knowledge of system architecture, technical debug & validation strategy
Be able to work in a high demand, fast paced environment with lots of real-time problem solving and critical thinking
**Requirements**
MS in Electrical Engineering or equivalent
10+ years of experience in in ASIC & FPGA design & debug
Knowledgeable of server system design and Architecture
Knowledge of logic design principles along with timing and power implications
Experience logic designer in Verilog or VHDL and familiar with ASIC or FPGA EDA tools
Knowledgeable in programming/scripting (C/C++, Perl, Python, ..)
Familiar with CPU and microcontroller designs, verification & debug
Familiar with cache coherency protocol, and their implementation, verification and debug.
Familiar with SOC, inra- and inter-chip interconnect systems
Familiar with current standard interfaces, PCIe, DRAM, Networking, CXL, ..
Must have good understanding and knowledge of high speed board design and layout
A great team player with Good attitude, aptitude with can do drive
This position is eligible for JoinCPBU referral campaign
This job may require the candidate to comply with travel restrictions and/or work from a facility that requires full vaccination prior to entry.
**Category :** Engineering and Technology
**Subcategory:** Software Engineering
**Experience:** Manager and Professional
**Full Time/ Part Time:** Full Time
**Posted Date:**
VMware Company Overview: At VMware, we believe that software has the power to unlock new opportunities for people and our planet. We look beyond the barriers of compromise to engineer new ways to make technologies work together seamlessly. Our cloud, mobility, and security software form a flexible, consistent digital foundation for securely delivering the apps, services and experiences that are transforming business innovation around the globe. At the core of what we do are our people who deeply value execution, passion, integrity, customers, and community. Shape whats possible today at
Equal Employment Opportunity Statement: VMware is an Equal Opportunity Employer and Prohibits Discrimination and Harassment of Any Kind: VMware is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. All employment decisions at VMware are based on business needs, job requirements and individual qualifications, without regard to race, color, religion or belief, national, social or ethnic origin, sex (including pregnancy), age, physical, mental or sensory disability, HIV Status, sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, past or present military service, family medical history or genetic information, family or parental status, or any other status protected by the laws or regulations in the locations where we operate. VMware will not tolerate discrimination or harassment based on any of these characteristics. VMware encourages applicants of all ages. Vmware will provide reasonable accommodation to employees who have protected disabilities consistent with local law.
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