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    Design Verification Engineer CPU - Stanford, United States - VMware

    VMware
    VMware Stanford, United States

    4 days ago

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    Description

    **Design Verification Engineer CPU & Server Platform**

    CAROUSEL_PARAGRAPH

    No

    Palo Alto, California

    Software Engineering

    R

    ** Share Job**

    mail_outlineGet future jobs matching this search

    or ** Job Description**

    **Business overview:**

    We are CPU & Server Platform team responsible for ESXi operating system and core virtualization infrastructure. In this role you will be part of Hardware team creating next generation HW accelerators that significantly influence Data center virtualization. You would join a cross-discipline team of highly capable and motivated engineers, designers and validators. You will have the opportunity to transform your ideas into World-changing technologies & Products for Datacenter growth . Work with Research Groups, Platform Engineering teams at all layers of Hardware & Software - from FPGA BS to Firmware to OS (ESXi) to Hypervisors. You will have the opportunity to influence external FPGA , Silicon & platform vendors and VMW partners.

    **What you are responsible for**

    Build and maintain a UVM verification environment for FPGA development, at both the block, and system levels that includes creating behavioral models to drive and check designs consisting of RTL, and third party IP blocks.

    Collaborate with the design team to develop test plans, and analyze the coverage

    Help build and maintain the simulation environment to efficiently run, collect results, in a timely and clear fashion

    Lead collaborative technical discussions to drive resolution on issues with internal teams and external HW partners

    Develop knowledge of system architecture, technical debug & validation strategy

    Be able to work in a high demand, fast paced environment with lots of real-time problem solving and critical thinking

    **Requirements**

    BS in Electrical Engineering or equivalent.

    5+ years of experience in ASIC/FPGA verification with UVM environments.

    Knowledge of logic design principles along with timing and power implications

    Fluency in system Verilog/UVM.

    Experience in Verilog simulators and coverage tools.

    Have developed random verification tests utilizing constrained-random, functional coverage, and assertion.

    Familiar with standards such as networking protocol, PCIE, and memory interfaces is a plus.

    Familiar with shell and scripting languages (Perl, Python , )

    Familiarity with SGE and similar is a plus

    C/C++ knowledge

    A great team player with Good attitude, aptitude with can do drive

    This job may require the candidate to comply with travel restrictions and/or work from a facility that requires full vaccination prior to entry.

    **Category :** Engineering and Technology

    **Subcategory:** Software Engineering

    **Experience:** Manager and Professional

    **Full Time/ Part Time:** Full Time

    **Posted Date:**

    VMware Company Overview: At VMware, we believe that software has the power to unlock new opportunities for people and our planet. We look beyond the barriers of compromise to engineer new ways to make technologies work together seamlessly. Our cloud, mobility, and security software form a flexible, consistent digital foundation for securely delivering the apps, services and experiences that are transforming business innovation around the globe. At the core of what we do are our people who deeply value execution, passion, integrity, customers, and community. Shape whats possible today at

    Equal Employment Opportunity Statement: VMware is an Equal Opportunity Employer and Prohibits Discrimination and Harassment of Any Kind: VMware is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. All employment decisions at VMware are based on business needs, job requirements and individual qualifications, without regard to race, color, religion or belief, national, social or ethnic origin, sex (including pregnancy), age, physical, mental or sensory disability, HIV Status, sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, past or present military service, family medical history or genetic information, family or parental status, or any other status protected by the laws or regulations in the locations where we operate. VMware will not tolerate discrimination or harassment based on any of these characteristics. VMware encourages applicants of all ages. Vmware will provide reasonable accommodation to employees who have protected disabilities consistent with local law.

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