ASIC Methodology Engineer - San Diego, CA

Qualcomm's Design Technology team is seeking a motivated engineer to drive development of advanced methodologies in die-level IR drop, STA. · Develop and drive analysis and optimization methodologies for interaction of IR drop and STADevelop physical-aware timing and IR drop ECO ...

Qualcomm's Design Technology team is seeking a motivated engineer to drive development of advanced methodologies in die-level IR drop, STA, and power. · ...

This is a job description for an Emulation Methodology Engineer at Qualcomm Technologies, Inc. · The team works closely with architects, designers, verification engineers, software engineers and customers. · ...

The DTECH team is part of the Global SOC organization responsible for STA methodology and signoff. · ...

We are seeking candidates with experience in emulation and silicon environments to work on the development and support of SoC pre-silicon platforms. · Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based em ...

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals.We have crafted a team of exceptional engineers stretching around the globe, · whose mission is to push the frontiers of what is possible today and define · the platfo ...

The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond. You will be working with physical design team (and other teams) on timing closure, CAD teams, IP team ...

As a Timing Engineer you will play a vital role in timing analysis targeting the Mobile Compute Automotive and IOT markets · The candidate will work with best-in-class methodologies tools and technology to design innovative SOC products at the block/IP-level and at system-level i ...

This role will help develop new flows/methodologies and algorithms to improve power, performance, and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. · ...

Job summaryAs a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implement ...

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals and drive to innovate new solutions. This position under Qualcomm's Global SOC organization offers the rare opportunity to have real impact in shaping 5G product lines ...

We're looking for a SoC Power Flow Methodology Engineer to join our team at Silicon Technologies. · Craft innovative solutions to intricate challenges in low-power chip design. · Develop AI-driven automated tools for efficient workflows.Solid grasp of VLSI designs and SOC design ...

Design adaptive power management controller on-chip sensor controller and digital power meter. Perform RTL design simulation synthesis timing analysis lint check clock domain crossing check conformal low power check and formal verification for IP blocks Work closely with technolo ...

Design adaptive power management controller on-chip sensor controller and digital power meter. · Perform RTL design simulation synthesis timing analysis lint check clock domain crossing check conformal low power check formal verification for IP blocks · ...

We are seeking a CAD & Methodology Engineer to develop, · enable, and support 3DIC and 2.5D physical design · and signoff methodologies for advanced multi-die systems.Develop,maintain,and qualify CAD flows for 3DIC · and 2.5D designs,including chiplets,interposers, · and advanced ...

We are seeking a CAD & Methodology Engineer to develop enable and support 3DIC and 2.5D physical design and signoff methodologies for advanced multi die systems. · This role focuses on building robust scalable and production ready flows spanning timing power IR/EM ESD thermal CFD ...

As an emulation and prototyping methodology automation expert at NXP Semiconductors in San Diego, CA. · Work closely with architecture teams IP designers and SoC implementation teams from multiple sites to develop advanced methodology automation for emulation prototyping enable p ...

We're seeking an experienced Physical Design Engineer with 10+ years of experience in ASIC design, place and route, and physical verification. · Lead physical design projects for complex SoC designs · Collaborate with cross-functional teams to drive design convergence · Develop a ...

+Do you love working on challenges that no one has solved yet and changing the game? · + · Description · In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP. · You are responsible for developing verification methodology suitable for ...

The RF Product Development and Test Engineering team is looking for an RF Bench Test Engineer to develop test solutions for highly integrated mobile wireless RF receivers... · Bench test system planning · SW development · ...