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    Senior ASIC Design Engineer - San Jose, United States - USA Tech Recruitment

    USA Tech Recruitment
    USA Tech Recruitment San Jose, United States

    24 minutes ago

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    Description

    Senior ASIC Design Engineer | AI Start-up | AI interference Solutions | San Jose

    Are you a Senior-level Design Engineer with experience, or looking to work, in Generative AI?

    This is an opportunity to join a highly funded and expanding startup, working on cutting-edge projects at the forefront of autonomous driving and AI

    As a senior member of the ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company's flagship perception module product.

    This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power.

    Responsibilities:

    • Author micro-architecture specifications and participate in specification and test plan reviews.
    • Architect and implement complex RTL designs.
    • Scope third-party IP requirements and solicit vendors.
    • Integrate CPU and other relevant IPs into the CPU sub-system.
    • Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
    • Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
    • Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.

    Qualifications:

    • 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
    • Experience in IP integration, specifically CPU IP into SoC.
    • Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
    • Familiarity with AMBA/APB/AXI Protocol
    • Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
    • Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.
    • Familiarity with low-power design. UPF flow for defining power intent of chips with multiple power domains
    • Previous experience with timing closure at high frequencies is a plus.
    • Interest in exploring AI architectures for convolution, transformer and other kinds of workloads

    What's on offer?

    • The opportunity to play a key role in shaping one of the most exciting and impactful startups globally, revolutionizing a future-defining market like autonomous driving.
    • Competitive benefits package including medical, vision, dental and an employee stock purchase plan.
    • Flexible work hours & generous PTO policy.

    If interested in this role please apply here or send your email directly to -

    By applying to this role, you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-).

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