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    Senior Reliability Engineer - Los Angeles, United States - ATR International

    ATR International
    ATR International Los Angeles, United States

    1 week ago

    Default job background
    Description
    We are seeking a Reliability Development Engineer for a very important client.

    Job Overview - Principal Duties and Responsibilities

    Successful candidate will be tasked for Product, Package reliability test tracking; reliability database, data analysis and summarization on a regular basis for commercial, industrial and/or automotive application Product reliability evaluation/qualification/monitor planning, execution and tracking for on-schedule product launch/monitor support Customer product reliability requirements database creation and management.

    Top 5 Required Skills

    • Product Reliability Test knowledge (HTOL, ESD, Latch-up, MSL, Temperature cycle, bias HAST, HTS)
    • HTOL hardware design and script bring up- verification.
    • PMIC ESD and latch-up setup experience
    • Burn-in oven (MCC, INCAL experience)
    • Fab and assembly process knowledge
    Technologies


    • Incal systems HWs and software experience
    • Scripts/vector debug

    Keywords:
    Product reliability, HTOL, ESD, Latch-up, MSL, Temperature cycle, bias HAST, HTS (High Temperature storage)

    Education Requirement:
    Bachelors degree in Electrical Engineering or higher, with Semiconductor Device Physics and VLSI design experience

    Minimum years of Experience Required


    • MUST HAVE 2 years' experience generating device qualification plans, performing reliability risk assessment as well as device level failure analysis.
    • MUST HAVE 4+ years experience with EIA/JEDEC/AEC standards for device qualification and test methods
    • MUST HAVE 5 years experience supporting reliability evaluation on Digital/RF products (micro-processor, network processor with embedded memory

    Additional Skills:

    • Strong IT/database experience/ skills Familiar with CMOS as well as Mixed Signal and RF/Analog circuit reliability stress techniques including HTOL, ESD and Latch-up.
    • Knowledge of device physics, IC fabrication, packaging technology and automotive (e.g. AEC-Q100) reliability qualification criteria
    #J-18808-Ljbffr
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