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    FIP Physical Design and QA Engineer - Phoenix, United States - Intel

    Intel
    Intel Phoenix, United States

    4 weeks ago

    Intel background
    Description

    Job Details:
    Job Description: Join Intel and build a better tomorrow.

    Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth.

    So, join us and help us create the next generation of technologies that will shape the future for decades to come.

    In this role you will be a key member of a team working to ensure that our Foundation IP (FIP) meets the highest quality standards.

    These IPs include memory compilers, standard cells, eFuse, and GPIO.

    In addition to the role, you will:

    • Create reference designs using Intel-designed Foundation IP .
    • Utilize industry standard tools to implement and run RTL to GDS flows to qualify FIPs.
    • Perform all aspects of the SoC design flow on these designs to ensure that the Foundation IP meet stringent quality requirements.

    Responsibilities for this position will include:

    • Scripting and automation of the physical design and debug flows.
    • Running internal IP QA flows on Foundation IP.
    • Development of new IP-level quality checks.
    • Interaction with EDA tool vendors to debug issues and develop QA flows, along with our internal Foundation IP development teams to summarize and debug issues.
    • Training and mentoring other team members to teach best practices for SoC design and debug.
    The ideal candidate should exhibit behavioral traits that indicate:

    • Ability to express effective written and verbal communications skills.
    • Highly organized with the ability to multi task and set priorities.
    • Problem-solving and analytical skills.
    • Perform effectively within team environments.
    • Continuous learning mindset.
    • Motivated and results orientated.

    What we offer:


    Intel provides opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.

    As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.

    We also offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).


    Our benefits promote a healthy, enjoyable life:

    excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work.

    We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.

    #DesignEnablementQualifications:

    You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


    Minimum Qualifications:


    Candidate will possess a BS degree with 4+ years of experience or MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical/Computer Engineering or a related field.4+ years of semiconductor industry experience.2+ years of experience with physical synthesis, place, and route using Synopsys Fusion Compiler or Cadence Genus/Innovus tools in advanced nodes (10nm or less).


    Preferred qualifications:
    4+ years of experience in the following areas:
    • Physical synthesis and place and route using Synopsys and Cadence tools.
    • Experience with end
    • to
    • end digital design flows and methodologies.
    • EDA tools, flows, and methodologies for SoC design and IP library development.
    • Scripting and automation of physical design flows.
    • An understanding of the IP EDA views/QA checks used for digital design flows
    • Experience interacting with vendors or customers.

    Job Type:

    Experienced HireShift:
    Shift 1 (United States of America)

    Primary Location:
    US, Texas, Austin

    Additional Locations:

    US, Arizona, Phoenix, US, California, San Diego, US, California, Santa Clara, US, Oregon, HillsboroBusiness group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.

    Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.


    Posting Statement:
    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance

    Position of TrustN/ABenefits:
    We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.

    Find more information about all of our Amazing Benefits here:

    Annual Salary Range for jobs which could be performed in US, California:$123,419.00-$185,123.00Salary range dependent on a number of factors including location and experience.

    Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

    In certain circumstances the work model may change to accommodate business needs.


    SummaryLocation:
    US, Texas, Austin; US, California, San Diego; US, Oregon, Hillsboro; US, California, Santa Clara; US, Arizona, PhoenixType: Full time
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