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    Principal Solutions Engineer - Mountain View, United States - Synopsys

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    Description
    Job Description and Requirements

    Emulation and Prototyping has become critical & indispensable part of SoC designs verification with growing design size and complexity. Shift Left on overall validation of the functional and performance intent of the ASIC/SoC/Chip DUT in a system level involving Application SW, drivers/SDK, Operating Systems of interest, Industry standard test/traffic/Exerciser & debug tools is the focus of Verification Solutions Product Engineering group. As a core part of this focus, we develop innovative solutions around Virtual transactors, third-party and/or customer specific test infrastructure.

    Looking for a Product Engineer to be part of Virtual Solutions Product Engineering Team to help drive PCIe, CXL VSA product deployments, working in close collaboration with customers, development & Product validation teams, leading to successful deployment of overall solution.

    Roles and Responsibilities:
    • Supporting the Synopsys Virtual System Adaptors for PCIe, CXL products
    • Responsible for debugging the protocol PCIe , CXL issues at RTL and system level.
    • Bring up of PCIe, CXL Virtual Host and Device Solutions on customer designs as needed working with AE teams.
    • Creating use cases / prototype designs based on customer needs and showcase the feasibility of solutions.
    • Track and debug customer issues and work with R&D team on issue resolution.
    • Managing the existing requests, assign appropriate priorities to bug fixes and new feature developments.
    • Managing the release process to ensure that the product is released on time and contains the enhancements that were planned.
    Requirements:
    • MS with 8+ or BS with 10+ Years of experience in Simulation, Emulation, Prototyping or ASIC design/verification.
    • Knowledge of key protocol's like PCIe, CXL, NVMe
    • Strong trouble shooting and problem-solving skills;
    • Experience in SoC design porting on emulators and/or prototyping solution, creating FPGA friendly interfaces, adoption of testbench environment and prototyping SoC environment w/ debug is highly preferred.
    • Domain knowledge in one or more areas: Networking, Storage, Automotive.
    • Working knowledge of C/C++/System C is a plus
    • Excellent customer interface, communication, and planning skills
    ABOUT US
    At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

    Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance-eliminating months off their project schedules.

    Stay Connected: Join our Talent Community

    Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

    The base salary range across the U.S. for this role is between $164,000-$246,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

    #LI-MS2

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