SoC Physical Design Engineer, STA/Timing - San Jose

We are looking for a STA Engineer to join our team. The successful candidate will be responsible for quality checks of incoming IPs and configuring the crosscheck tool to filter out real violations and flag QA issues. · Timing expert preferably w/ Siemens Fractal/Crosscheck tool ...

Job Description: · ◦ Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. · ◦ Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and powe ...

Job Description: · ◦ Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. · ◦ Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and powe ...

The job involves overseeing fullchip SDCs and working with physical design and DFT teams to close fullchip timing in multiple timing modes. · Member of design team who oversees fullchip SDCs. · ...

+Member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. · ++Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block lev ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology. · Coverage medical and dental · Retirement benefits · ...

This role involves leading edge IP development and coordinating with multiple SOC teams. As an ASIC STA Engineer you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. Yo ...

This is a full-time role for a Senior Physical Design Engineer/STA located in California. · Perform full-chip and block-level static timing analysis for advanced ASIC designs. · ...

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Sed sit amet nulla auctor, vestibulum magna sed, · Bachelors or Masters degree in computer engineering/Electrical Engineering. · ...

+ WHAT YOU DO AT AMD CHANGES EVERYTHING+ At AMD,+ our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers,+ to PCs,+ gaming and embedded systems.+ Grounded in a culture of innovation and collaboration,+ we believe real ...

Join us to help deliver the next groundbreaking Apple product. · Play a major role analyzing the design and driving fixes as well as developing,maintaining and improving our Lint,Clock Domain Crossing (CDC),Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints ...

+Job summary · +Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, · +and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. · +Dynamic, intelligen ...

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. · ...

· Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networ ...

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networkin ...

We're seeking an experienced Frontend Synthesis/STA Engineer to join our team. · Design and implement digital circuits using Verilog or VHDL. · Perform synthesis and optimization of digital designs. · Conduct static timing analysis (STA) to ensure design meets timing requirements ...

We are Synopsys. We drive innovations that shape how we live and connect. Our technology powers the Era of Pervasive Intelligence. Join us to transform the future through continuous technological innovation. · Technically lead and manage local and remote teams for complex Subsyst ...

We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff. The ideal candidate will have a strong track record of driving projects to tapeout, excellent communication skills, ...

Perform full-chip Static Timing Analysis (STA). · Develop, validate, and own SDC constraints based on architectural and micro-architecture specifications. · Define and manage primary/generated clocks, IO delays, case analysis, false paths, multicycle paths, and other timing excep ...

Altera is looking for a Timing Engineer to lead timing activities for a subsystem. · ...