Principal Engineer, Device Modeling - San Jose

Only for registered members San Jose, United States

2 weeks ago

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Full time $219,000 - $351,000 (USD)
+ Develop and analyze new CMOS and beyond-CMOS device architectures
+ Develop internal benchmarking capability based on available data
+ Conceptualize design assess new CMOS device architectures+
Preferred skills include experience in developing new CMOS device architectures understanding of FEOL MOL BEOL process flows and experience in designing logic test structures.
The pay range below is for all roles at this level across all US locations and functions Individual pay rates depend on a number of factors including role function location knowledge skills experience education training We also offer incentive opportunities that reward employees based on individual company performance This is in addition to our diverse package of benefits centered around wellbeing employees loved ones In addition usual Medical Dental Vision 401k our inclusive rewards plan empowers people care whole selves An investment future ours Give Back With charitable giving match frequent opportunities get involved take active role supporting community Enjoy Time Away start 4 weeks paid time off year plus holidays sick leave rest recharge Care Family whatever family means support along way including stipend fertility care adoption medical travel support virtual vet care fur babies Prioritize Emotional Wellness demand apps free confidential therapy sessions have support matter where you are Stay Fit eating well being active important healthy life onsite Cafe gym virtual classes make easier Embrace Flexibility Benefits best when space use them facilitate flexible environment find right balance you Job summary
  • This position requires experienced technologists who will independently research explore future logic technology paths capabilities applications through design/system-technology optimization.

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