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    Design Engineer - San Diego, United States - Infobahn Softworld

    Infobahn Softworld
    Infobahn Softworld San Diego, United States

    1 week ago

    Default job background
    Description

    JOB DUTIES:

    • Responsible for RTL design using Verilog HDL for implementation and debug.
    • Read and comprehend System on Chip level architectural specification.
    • Write microarchitecture specification for new and modified functions.
    • Responsible for linting and simulation of design.
    • Work with synthesis and backend teams for physical implementation.

    Make your application after reading the following skill and qualification requirements for this position.

    KEY RESPONSIBILITIES:

    • Perform RTL design of digital components in Verilog/systemverilog.
    • Analyze/fix Lint and CDC errors of the components.
    • Help to improve/automate design process.

    PREFERRED EXPERIENCE:

    • Knowledge of RISK-V processor integration Express
    • Multi-clock domain designs.
    • Design constraints for synthesis and static timing analysis.
    • Knowledge of AXI/AMBA protocol
    • Knowledge of front-end RTL design tools and methodologies.
    • Knowledge of scripting languages like Perl, TCL or cshell

    EDUCATION:

    Bachelor's or Master's in Computer Engineering

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