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Staff FPGA Design Engineer - California, United States - Recruiting from Scratch
Description
nWho is Recruiting from Scratch:
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Recruiting from Scratch is a talent firm that focuses on placing the best candidate for our clients.
Our team is 100% remote and we work with teams across North America, South America, and Europe to help them hire.
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About our Client
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Our client is building a distributed radar imaging constellation to power the first accurate, real-time 3D model of the world.
As an FPGA Design Engineer in the Hardware Engineering team, you will create solutions on our FPGA platform to support radar and communications payload as well as our ground infrastructure.
You will work with Communication Systems and Radar Algorithms teams to define, implement, and test various algorithms, control systems, and modem systems on our FPGA platform.
The role requires implementing proprietary algorithms and integrating third-party IPs on the FPGA platform.This is a unique opportunity to join our early team and make a significant impact by contributing to the creation of a brand-new platform free from any legacy limitations.
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Responsibilities:
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Collaborate with Radar, Communications, and RF engineers to define, implement, and test various signal processing algorithms and digital logic functions in FPGAs
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Work with HW Design Engineers and Embedded SW engineers to rapidly prototype and bring up satellite payloads that combine FPGA, processors, firmware, sensors, and networking functionality
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Take full responsibility for executing RTL design with or without HLS (High-Level Synthesis), physical implementation, timing closure, and validation through simulation
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Create robust software infrastructure using modern coding techniques to ensure that FPGA images seamlessly integrate into our hardware platformu0027s Board Support Package while also functioning independently
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Basic Qualifications:
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B.S in Electrical or Computer Engineeringu0026
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11+ years of experience in modern FPGA design, implementation, and verification
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Solid understanding of FPGA logic Synthesis, partitioning, routing and timing closure
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Excellent teamwork and communication skills
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Learns new concepts rapidly, completely, and in a self-directed manner
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High levels of self-motivation and personal accountability
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Ability to work in a fast-paced environment under significant time constraints
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Experience in FPGA or ASIC design in VHDL, Verilog, or SystemVerilog
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Experience with FPGA tools, preferably Xilinx Vivado
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Preferred Skills and Experience:
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Masteru0027s degree in Electrical or Computer Engineering
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6+ years of FPGA prototyping experience (compilation, debugging and throughput tuning) on Xilinx/Altera/Lattice Semiconductor FGPAs
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Strong logic design, RTL coding (Verilog / VHDL), and debugging skills
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Familiar with design constraints, logic synthesis, timing closure analysis, and clock/reset domain crossing checks
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Proficiency with FPGA synthesis and implementation tools (e.g. Xilinx Vivado, Altera Quartus II),u0026 HDL simulators (VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), and Power Analysis tools.
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Experience implementing fixed-point DSP blocks in RTL, such as IIR and FIR filters, modulator/demodulator, encoder/decoders PLLs, CORDIC operations and FFT processors, and CORDIC processors
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Familiarity with custom IP verification and integration
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Experience creating UVM-based test benches for verification of FPGA designs
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Familiarity with processor architecture and associated communications protocols such as AXI, DMA, I2C, UART, SPI, PCIE, USB, and Ethernet.
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Proficiency in scripting languages such as Python and Bash
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Experience with high-speed SERDES interfaces, Ethernet, and IP networking
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ITAR Requirements:
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To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
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Location:
Palo Alto, CA
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Salary:
$150,000-$215,000 a year + equity
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