- Bachelor's or Master's in Computer Engineering
- Perform RTL design of digital components in Verilog/systemverilog.
- Analyze/fix Lint and CDC errors of the components.
- Guarantee quality/timely deliverables meeting project's schedule.
- Help to improve/automate design process.
- SoC Architecture
- Knowledge AND hand-on experience from industry ASIC design flow including RTL coding
- Arteris FlexNoc IP configuration and integration, debugging/verification, and supporting synthesis and timing closure will be a plus.
- Knowledge of RISK-V processor integration Express
- Multi-clock domain designs.
- Design constraints for synthesis and static timing analysis.
- Knowledge of AXI/AMBA protocol
- Knowledge of front-end RTL design tools and methodologies.
- Knowledge of scripting languages like Perl, tcl or cshell
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ASIC FPGA RTL Design Engineer - San Diego, United States - Droisys
Description
Droisys is an innovation technology company focused on helping companies accelerate their digital initiatives from strategy and planning through execution. We leverage deep technical expertise, Agile methodologies, and data-driven intelligence to modernize systems of engagement and simplify human/tech interaction.
Check you match the skill requirements for this role, as well as associated experience, then apply with your CV below.
Amazing things happen when we work in environments where everyone feels a true sense of belonging and when candidates have the requisite skills and opportunities to succeed. At Droisys, we invest in our talent and support career growth, and we are always on the lookout for amazing talent who can contribute to our growth by delivering top results for our clients. Join us to challenge yourself and accomplish work that matters.
Client Description
Our client is a major Fortune 500 company and one of the world's most innovative and cutting-edge technology companies, and this role is in the Interactive department.
Droisys is seeking ASIC FPGARTL Design Engineer job offering hybrid onsite work for a long-term job opportunity in Santa Clara, CA and San Jose, CA area of the USA.
Job Title ASIC FPGA RTL Design Engineer
Job Location San Jose, CA or Santa Clara, CA [Onsite Work]
Job Description
Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.
EDUCATION
KEY RESPONSIBILITIES
PREFERRED EXPERIENCE
Droisys is an equal opportunity employer. We do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. Droisys believes in diversity, inclusion, and belonging, and we are committed to fostering a diverse work environment.