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    Senior Design Verification Engineer - Austin, United States - Tessolve

    Tessolve
    Tessolve Austin, United States

    1 week ago

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    Description

    Job Title: Senior Design Verification Engineer

    Location: Austin, Texas

    About Company : Tessolve Semiconductor is a leading provider of semiconductor engineering solutions, offering a comprehensive suite of services to semiconductor companies worldwide. Our mission is to deliver innovative solutions that enable our clients to bring their products to market faster and more efficiently.

    Position Overview

    We are seeking a highly skilled Senior Design Verification Engineer with a minimum of 6 years of experience to join our dynamic team in Austin, Texas. The ideal candidate will have a strong background in SOC level design verification, proficient in System Verilog and UVM methodologies, and possess a deep understanding of the full verification flow including coverage closure. Additionally, expertise in low-level programming languages such as C and Assembler, along with experience in system verification using C, are highly desirable. Knowledge of AMBA protocols (AXI, AHB, APB) and CHI protocol is a definite plus.

    Key Responsibilities:

    Develop and execute test plans for SOC level verification, ensuring comprehensive coverage of all functional requirements.

    Collaborate with cross-functional teams to define verification strategies and methodologies.

    Implement verification environments using System Verilog and UVM.

    Perform low-level programming tasks in C and Assembler for hardware/software co-verification.

    Conduct system-level verification using C-based methodologies.

    Analyze and debug failures, and work closely with design teams to resolve issues.

    Drive coverage closure and verification sign-off.

    Qualifications:

    Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

    6+ years of experience in Design Verification, with a focus on SOC level verification.

    Proficiency in System Verilog and UVM methodologies.

    Strong knowledge of test plan creation and tracking.

    Experience with full verification flow including coverage closure.

    Proficient in low-level programming languages such as C and Assembler.

    Experience in system verification using C.

    Familiarity with AMBA protocols (AXI, AHB, APB) and CHI protocol is advantageous.

    Excellent problem-solving skills and attention to detail.

    Strong communication and collaboration skills.

    Disclaimer : At Tessolve, we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.

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