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    Design Verification Engineer - New York, United States - Zenex Partners

    Zenex Partners
    Zenex Partners New York, United States

    3 weeks ago

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    Description

    Position Title:
    Design Verification Engineer (GPU Subsystems)

    Department:
    Technical


    Location:
    Austin, Texas Metropolitan Area

    Position Type:
    Extendable contact for 12 month

    Role type :
    W2, C2C and 1099

    Description:

    As a Design Verification Engineer, you will play a pivotal role in ensuring the functional verification of GPU Subsystems, including Shader, Texture, and Memory Systems.

    This role involves triaging regression failures, debugging functional errors in RTL models, and maintaining efficient regression status.

    You will contribute to the development of Scalable SystemVerilog/UVM test benches and collaborate closely with Architects and RTL designers to ensure comprehensive verification coverage.


    Responsibilities:
    Triage regression failures and implement necessary testbench updates.
    Debug functional errors in RTL models using simulation and debug tools.
    Maintain efficient and clean regression status.
    Develop Scalable SystemVerilog/UVM testbenches for unit and/or Cluster level verification.
    Review Architecture and Micro-Architecture specifications.
    Work closely with Architects and RTL designers.
    Define, maintain, and execute unit and/or Cluster level verification test plans.
    Generate and execute test cases on logic simulation models.
    Code Functional coverage models and System Verilog assertions.
    Drive Functional Coverage and Code coverage to closure.
    Integrate C++ reference models into Scoreboards.


    Requirements:
    5-15 years of industry experience in a design verification role.
    Proficiency in System Verilog/UVM/OVM, OOP/C++.
    Knowledge of GPU, and experience with Shader, Texture, or Memory Systems a plus.
    Experience with code coverage and functional coverage-driven verification methodology.
    Experience in creating, running, and debugging SystemVerilog/UVM constraint-random Testbenches.
    Excellent working knowledge of scripting languages such as Python or Perl.
    Understanding of micro-architecture, logic design, FSMs, and arithmetic datapath pipelines.
    Strong functional verification experience including Test planning, Testbench Architecture, and Test/Coverage Model/Assertion Development.
    Strong debugging skills.
    Strong programming skills with a good understanding of algorithms and data structures.
    Good verbal and written communication skills.
    Additional

    Requirements:
    Familiarity with current state-of-the-art testbench development such as UVM methodology.
    Experience in design verification with UVM and SystemVerilog is a MUST.
    Hybrid onsite presence is required 3 times per week.
    Intrested candidates can directly call me @
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