- BS/MS in EE/computer science or equivalent experience
- 3- 5+ years' experience,
- Good understanding in VLSI digital design/Layout/Timing closure
- Basic knowledge on circuit design, device delays, and timing at gate-level
- Familiar with industry EDA tools such as Cadence Innovus/Quantus/Tempus, Synopsys Fusion Compiler/ICC2/StarRC/Primetime and Mentor Calibre.
- Proficient programming and scripting skills (Perl, Python, TCL, C-shell, make)
- Hardware Design Languages like Verilog, VHDL
- Self-motivated team worker, good verbal and written interpersonal skills.
- Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC would be an added advantage.
- Solid understanding of hierarchical physical design strategies, methodologies and nanometer advanced node technology issues.
- Hands-on experience in STA including multi-mode multi-corner analysis and ability to analyze and fix critical timing issues.
- Proven track record of delivering tape-out quality GDSII with silicon success in sub 10 nm is a plus.
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Intel Corporation Santa Clara, CA, United StatesIntel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. Join us, because at Intel, we are building a better tomorrow. Intel NEX Cloud ...
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Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Broadcom's Timing Sign-Off g ...
Sr./Staff Physical Design Engineer - Santa Clara, United States - Ambarella
Description
Job DescriptionResponsibilities:
The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella's cutting edge low power AI SoC from Netlist to GDSII.
The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.
Requirements
Sr./Staff Physical Design Engineer professionals in Santa Clara
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Jahnvi Mehta
Looking for Physical Design/STA internship
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Paulina Casillas Topete
Project Planner