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    Senior DFT Staff Engineer - Phoenix, United States - Mastech Digital

    Mastech Digital
    Mastech Digital Phoenix, United States

    2 weeks ago

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    Description

    Job Description

    Job Description

    Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Senior DFT Staff Engineer for our client in the IT-Services domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position, and the client is looking for someone to start immediately.

    Duration: 6+ Months Contract

    Location: Phoenix AZ

    Role: Senior DFT Staff Engineer

    Primary Skills: Electrical Engineering

    Role Description: As a Senior DFT Staff Engineer, you must have at least 8+ years of experience. For this role, you must have the ability to distill the requirements from the various block and chip lead, write the specification and write the RTL for all necessary wrapper and control logic.

    Minimum 3-7 years' experience in semiconductor design and development.

    Must Have Skills:

    -3-7 years of experience required for each skill.

    Electrical Engineering

    Electronic Design Automation (EDA)

    Semiconductor Design & Development

    Nice-to-Have Skills:

    Developing DFT specifications

    Industry standard DFT and design tools

    Debugging ATPG/MBIST patterns

    Responsibilities:

    Work with teams to document the DFT specifications and define the requirements.

    Develop and implement DFT architecture and infrastructure.

    Develop and drive execution of enhanced DFX (DFT/Design-For-Debug) methodologies, with increased focus on debug support.

    Work with the DV team to verify DFT implementations.

    Generate structural test vectors, analyze, and improve coverage/test time/test cost.

    Work with designers on STA, physical, power, and logical issues impacting DFT.

    Work with test engineers to bring up test vectors on silicon.

    Work with lab bring-up teams to bring up test vectors in the lab environment.

    Manage schedules and support internal and external cross-functional/cross-organizational engineering efforts.

    Here's what you need:

    A minimum of three years of experience with Hardware Design-For-Test (DFT) engineering including

    A minimum of three 3 years of experience in uP and/or GPU and/or Video Processing

    Bachelor's Degree or equivalent (12 years) work experience ( Associate's Degree with 6 years of work experience)

    Bonus points if:

    Developing DFT specifications

    -Industry standard DFT and design tools

    Debugging ATPG/MBIST patterns

    STA constraints and their interaction with DFT

    Experience with Root Cause Analysis

    IP/Top Scan insertion (all EDA solutions)

    IP/ Top Mbist insertion (all EDA solutions)

    Scripting languages TCL/Perl/Python

    Experience with Synopsys DFT tools (Tetramax, DFT compiler, BSD compiler, Formality, Spyglass)

    Experience with JTAG and IEEE standards and

    Education: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent

    Experience: Minimum 8+ years of experience

    Relocation: This position will not cover relocation expenses

    Travel: No

    Local Preferred: Yes

    Note: Must be able to work on a W2 basis (No C2C)

    Recruiter Name: Aakash Chauhan

    Recruiter Phone: Ext: 2842)

    Equal Employment Opportunity

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