Harshith Reddy Surakanti

As a Hardware Design Engineer, I designed and verified RTL/IP modules with a strong focus on FPGAs and SoCs. I integrated IPs and hardware accelerators with Python running on embedded ARM cores, achieving a 40% reduction in latency. I also automated FPGA workflows using TCL scripts, gaining hands-on experience in both front-end and back-end tools. This included performing linting, applying low-power design techniques, and conducting Static Timing Analysis (STA), Place-and-Route (PnR), Clock Domain Crossing (CDC), and routing checks. My efforts contributed to the successful completion of three tape-outs.

I have also worked as a Senior Software Development Engineer at NTT DATA, I enhanced ETL scripts for data extraction from SQL Server, improving data integration processes significantly. I designed, implemented, and maintained high-performance ETL workflows, ensuring efficient data handling across various systems. Additionally, I focused on automating processes and ensuring data integrity from multiple sources, leading to optimized workflows and improved data management.

Masters in VLSI at Purdue University