About CHUN-JU LIN:
Chun-Ju Lin
Skills :
- ASIC / VLSI Cell‑based circuit design, Physical Design, Full‑Custom circuit design, Analog circuit design SI / PI IBIS model, Jitter analysis, eye‑diagram analysis, Power Integrity validation, Stack‑up model Tools Verilog, Innovus, Design Compiler, PrimeTime, Hspice, Laker, Ansys HFSS, PowerDC, C/C++, python
Education :
- California Institute of Technology Pasadena, CA
- Master of Science in Electrical Engineering Aug. 2023 ‑ Dec. 2024
- Concentration: ASIC/VLSI.
- National Tsing Hua University Hsinchu, Taiwan
- Bachelor of Science in Electrical Engineering Sep. 2019 ‑ Jun. 2023
- GPA: 4.19/4.3, rank: 3/53
- Concentration: ASIC/VLSI, Computer Architecture.
- Key Coursework: Advanced Physical Design, VLSI circuit Design, Analog circuit design, IC Design.
Work Experience:
- Amazon Development Center Taiwan Limited Taipei
- Taiwan Hardware Dev Engineer, Intern Jul. 2022 ‑ Jul. 2023
- Designed and developed a target signal reconstruction algorithm utilizing advanced reflection cancellation methods, effectively mitigating up to 70 % of signal distortion during measurements.
- Validated and verified the power and signal integrity of Amazon Ring products through comprehensive assessments, including rigorous analysis of factors such as IR drop, jitter, and eye‑diagram evaluations.
- Created an automated power analysis tool with versatile functionalities, including component deactivation, VRM configuration, and sink creation, simplifying and accelerating the power analysis process.
- Conducted thorough testing and validation of the PIR sensor routing rule for Amazon Ring products, ensuring its effectiveness and accuracy in PCB layout designs.
Projects:
- N16 FinFET ResNet CNN Accelerator with Low Power Design
- Jan. 2023 ‑ Jun. 2023
- Achieved 60% area utilization and a remarkable 85% reduction in leakage power during the rest‑macro stage.
- Implemented the efficient Systolic Array architecture to harness increased computing power. • Established a Low‑Power Bottom‑Up synthesis and APR (Automatic Place and Route) flow.
- Designed Floorplan and PowerPlan for optimal C4 bump and SRAM arrangement.
- Utilized Calibre for sign‑off tasks, LVS (Layout vs. Schematic), and DRC (Design Rule Check).
- Image de‑noise hardware implementation by CORDIC Jacobi SVD Oct. 2022 ‑ Nov. 2022
- Achieved an impressive 73% area utilization, resulting in a significant improvement of 2.75dB in the Peak Signal-to-Noise Ratio (PSNR).
- Undertook the objective of developing a de‑noise chip for 320x480 images.
- Implemented the CORDIC Jacobi SVD algorithm to create a hardware‑friendly system.
- Completed the full Automatic Place and Route (APR) process using a 0.18um CMOS process.
- Read‑Only Memory Circuit Design Aug. 2021 ‑ Jan. 2022
- Conducted rigorous verification of the ROM design, achieving an impressive access time of 2.535ns while maintaining a compact layout area of 13357um squares.
- Developed a Full‑Custom circuit design for a 64x16 Read‑Only Memory (ROM) optimized for low energy consumption and optimal layout area, leveraging the advantages of the 0.18um CMOS process.
Publications
- Chun‑Ju Lin, C. J. Lin, S. Lee. Target signal reconstruction by reflection cancellation method to distortion signal from measurement. IEEE EMC+SIPI 2023.
Experience
Work Experience:
- Amazon Development Center Taiwan Limited Taipei
- Taiwan Hardware Dev Engineer, Intern Jul. 2022 ‑ Jul. 2023
- Designed and developed a target signal reconstruction algorithm utilizing advanced reflection cancellation methods, effectively mitigating up to 70 % of signal distortion during measurements.
- Validated and verified the power and signal integrity of Amazon Ring products through comprehensive assessments, including rigorous analysis of factors such as IR drop, jitter, and eye‑diagram evaluations.
- Created an automated power analysis tool with versatile functionalities, including component deactivation, VRM configuration, and sink creation, simplifying and accelerating the power analysis process.
- Conducted thorough testing and validation of the PIR sensor routing rule for Amazon Ring products, ensuring its effectiveness and accuracy in PCB layout designs.
Education
Education :
- California Institute of Technology Pasadena, CA
- Master of Science in Electrical Engineering Aug. 2023 ‑ Dec. 2024
- Concentration: ASIC/VLSI.
- National Tsing Hua University Hsinchu, Taiwan
- Bachelor of Science in Electrical Engineering Sep. 2019 ‑ Jun. 2023
- GPA: 4.19/4.3, rank: 3/53
- Concentration: ASIC/VLSI, Computer Architecture.
- Key Coursework: Advanced Physical Design, VLSI circuit Design, Analog circuit design, IC Design.
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