Bilal Khan

ASIC Verification Engineer with hands-on experience in coverage-driven verification and assertion-based verification using UVM methodology and SystemVerilog. Specialized in developing testbench architectures, Verification IP integration (Synopsys AMBA VIP), and verification for AMBA APB/AXI, SPI, and I2C protocols. Proven ability to achieve 95% functional coverage and reduce debug time by 40% through systematic root-cause analysis and constrained random testing. Strong collaborator with cross-functional teams including design, architecture, and validation engineers to ensure first-pass silicon success.

ASIC Design Verification Intern (ChipEdge Technologies) [Mar' 25 – Aug' 25]

▪ Developed testbench architecture using UVM methodology for ASIC IP blocks with Synopsys VIP integration, creating reusable verification components (drivers, monitors, scoreboards, sequences) that improved modularity by 25% and accelerated project efficiency by 15%.

▪ Executed coverage-driven verification of AMBA APB/AXI protocols using constrained random testing and directed test cases, achieving 95% functional coverage and 100% code coverage. Developed functional coverage models to track verification progress and identify coverage holes.

▪ Implemented assertion-based verification using SystemVerilog Assertions (SVA) for protocol compliance checking of SPI/I2C interfaces, reducing integration issues by 30% through early detection of design violations.

▪ Performed systematic debug and root-cause analysis of RTL failures using Synopsys Verdi waveform debugging, reducing debug time by 40%. Analyzed simulation logs, identified failure patterns, and collaborated with design team to resolve issues.

▪ Automated regression testing workflow using Python and Perl scripts for nightly builds and coverage tracking. Utilized verification tools (VCS, Questa Sim, DVE) for simulation and coverage assessment.

▪ Collaborated closely with cross-functional teams including RTL designers and architects in design reviews, test plan development, and functional sign-off. Contributed to verification planning and created detailed test plans for IP verification.

Graduate Research & Teaching Assistant [Sep' 23 – Dec' 25]

Northern Illinois University – DeKalb, Illinois

▪ Published 4 peer-reviewed papers on low-power CMOS design and organic electrochemical transistors. Designed full-swing restored CMOS full-adder achieving 30% power reduction through transistor-level optimization and PVT corner analysis.

▪ Mentored 50+ students in digital design, circuit analysis, and computer architecture. Collaborated with students on lab experiments, providing hands-on guidance in troubleshooting and debugging circuit implementations.

Full Stack Developer Intern (QT Business Solutions) [Nov' 22 – Apr' 23]

▪ Developed applications in Java/C++ and optimized MySQL databases, demonstrating strong programming and problem-solving skills.

M.S., Electrical Engineering (Dec 2025)

Northern Illinois University, DeKalb, Illinois

B.E., Electrical and Communication Engineering (June 2023)

Osmania University, Hyderabad, India