- Develop UVM Agents for proprietary buses
- Instantiate VIPs for industry standard buses
- Work in both block-level/chip-level UVM testbench environment
- Work with RTL designers to resolve simulation issues
- Implement cover groups according to design requirements
- Work on code and functional coverage closures to achieve 100%
- Perform code reviews and to mentor junior engineers in the group
- BS degree with 15 years' experience
- Fluent in SystemVerilog including SVA
- Recent experience with UVM/UVMF
- Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
- Familiarity with at least one IEEE bus standard
- Experience with DDR3/DDR4, Amba Axi protocols
- Firm grasp of constrained-random testing and coverage-driven verification
- Experience with formal analysis
- Practice using Python, Perl, Bash or other scripting languages
- Ability to work in a Linux environment
- Strong analysis and problem-solving skills
- The ability to obtain a US secret clearance is required which requires proof of US citizenship
- Active secret clearance is preferred
-
Design Verification Engineer
4 days ago
Apple Watertown, United StatesDesign Verification Engineer · Waltham,Massachusetts,United States · Hardware · At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for ...
-
Staff Design Verification Engineer
1 week ago
Lightmatter Boston, Massachusetts, United States PermanentStaff Design Verification Engineer · Lightmatter is a photonic computer company redefining what computers and human beings are capable of by building engines that will power discoveries and drive progress in a sustainable way. With modern human progress relying heavily on compute ...
-
Staff Design Verification Engineer
1 week ago
Lightmatter Boston, United StatesJob Description · Job DescriptionStaff Design Verification Engineer · Lightmatter is a photonic computer company redefining what computers and human beings are capable of by building engines that will power discoveries and drive progress in a sustainable way. With modern human pr ...
-
Sr. Digital Design Verification Engineer
1 week ago
GCR Professional Services Cambridge, MA, United StatesSr. Digital Design Verification Engineer · Direct Hire · FTE, Full Benefits... Hybrid, Onsite Cambridge, MA · Security Requirement: · The ability to obtain a US secret clearance is required which requires proof of US citizenship Active secret clearance is preferred · Digital Desi ...
-
Senior UVM Digital Verification Engineer
2 weeks ago
GCR Professional Services Cambridge, United StatesSenior UVM Digital Verification Engineer · While professional experience and qualifications are key for this role, make sure to check you have the preferable soft skills before applying if required. · Direct Hire · FTE, Full Benefits... Remote · Mulitple Openings · Security ...
-
Lead Digital Design Verification Engineer
2 weeks ago
Softworld Inc Cambridge, MA, United StatesJob Title: ASIC/FPGA Verification Engineer - UVM · Job Location: Cambridge MA remote work is available) · Onsite Requirements: · UVM · System Verilog · FPGA/ASIC · Job Description: · The Client is seeking a motivated and experienced Senior Verification Engineer to tackle no ...
-
Senior UVM Digital Verification Engineer
2 weeks ago
GCR Professional Services Cambridge, United StatesSenior UVM Digital Verification Engineer · Direct Hire · FTE, Full Remote · Mulitple Openings · Security Requirement : The ability to obtain a US secret clearance is required which requires proof of US citizenship · Active secret clearance is preferred ...
-
Senior UVM Digital Verification Engineer
1 week ago
GCR Professional Services Cambridge, United StatesSenior UVM Digital Verification Engineer · Direct Hire · FTE, Full Benefits... Remote · Mulitple Openings · Security Requirement: · The ability to obtain a US secret clearance is required which requires proof of US citizenship · Active secret clearance is preferred · Digital Des ...
-
Senior UVM Digital Verification Engineer
3 weeks ago
The Charles Stark Draper Laboratory Inc Cambridge, United StatesOverview · Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space explo ...
-
FPGA Verification Engineer
3 weeks ago
Selby Jennings Boston, United StatesJob Description: · Develop and execute high-performance FPGA-based computing and networking solutions utilized within electronic trading environments · Develop testbenches and execute verification plans to ensure the correctness of designs. · Create testbenches and carry out veri ...
-
Design Verification Engineer
1 day ago
Apple Waltham, United StatesSummary · Posted: Jun 17, 2024 · Role Number: · At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually t ...
-
Senior UVM Digital Verification Engineer
4 weeks ago
GCR Professional Services Cambridge, United StatesSenior UVM Digital Verification Engineer · Direct Hire · FTE, Full Benefits... Remote · Security Requirement: · The ability to obtain a US secret clearance is required which requires proof of US citizenship Active secret clearance is preferred · Digital Design Team is seeking a ...
-
Design Verification Engineering
4 days ago
General Dynamics Mission Systems Dedham, MA, United StatesRequires a Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field. Department of Defense Secret security clearance is required at time of hire. Due to the nature of work performed within our facilities, U.Sign on Bonus up t ...
-
Senior UVM Digital Verification Engineer
3 weeks ago
GCR Professional Services San Francisco, United States PermanentSenior UVM Digital Verification Engineer · Direct Hire · FTE, Full Remote · Security Requirement:The ability to obtain a US secret clearance is required which requires proof of US citizenship · Active secret clearance is preferred · Digit ...
-
Senior UVM Digital Verification Engineer
3 weeks ago
The Charles Stark Draper Laboratory Inc Cambridge, United StatesOverview · Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space explor ...
-
Principal UVM Digital Verification Engineer
3 weeks ago
Draper Labs Cambridge, United StatesPrincipal UVM Digital Verification Engineer (Remote) · Job Location · US-MA-Cambridge · Requisition ID · Overview · Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national c ...
-
Senior UVM Digital Verification Engineer
3 weeks ago
Draper Labs Cambridge, United States· Senior UVM Digital Verification Engineer (Remote) · Job Location · US-MA-Cambridge · Requisition ID · Overview · Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national chal ...
-
Hardware Verification Engineer
1 week ago
Teradyne North Reading, United StatesTeradyne is a global leader in the manufacturing of Automated Test Equipment (ATE). Behind every electronics device you use, Teradyne's leading-edge test technology ensures your device works right the first time. Our portfolio of automation solutions helps manufacturers develop a ...
-
Design Verification Engineer
6 days ago
Einfochips Maynard, United StatesJob Title: Senior Design Verification Engineer (eInfochips Inc.) · What You'll Be Doing: · At-least 10+ years of experience in System Verilog HVL and C++/C · At-least 10+ year of experience in UVM. · Experience in complete verification cycle which includes development of test pla ...
-
Design Verification Engineer
1 day ago
Einfochips Maynard, United StatesJob Title: Senior Design Verification Engineer (eInfochips Inc.) · What Youll Be Doing: · At-least 10+ years of experience in System Verilog HVL and C++/C · At-least 10+ year of experience in UVM. · Experience in complete verification cycle which includes development of test ...
Principal UVM Digital Verification Engineer - Cambridge, United States - Draper Labs
![Default job background](https://contents.bebee.com/public/img/bg-user-ex-1.jpg)
Description
Principal UVM Digital Verification Engineer (Remote)
Job Location
US-MA-Cambridge
Requisition ID
Overview
Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit
Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. If this specific job opportunity and the chance to work at a nationally renowned R&D innovation company appeals to you, apply now
Equal Employment Opportunity
Draper is committed to creating a diverse environment and is proud to be an affirmative action and equal opportunity employer. We understand the value of diversity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, gender identity, national origin, veteran status, or genetic information.
Draper is committed to providing access, equal opportunity and reasonable accommodation for individuals with disabilities in employment, its services, programs, and activities. To request reasonable accommodation, please contact
ResponsibilitiesDraper's Digital Design Team is seeking a motivated and experienced Principal UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.
You will develop verification approaches, author and execute verification plans, and use formal analysis tools. While leading verification teams, you will define the test-bench architecture and verification approach. You will be responsible for developing methodologies and defining processes used by verification teams. You will also have the opportunity to lead multi-disciplinary teams and learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.
Duties and Responsibilities
- Develop verification and test plans
Required Qualifications:
Security Requirement:
Location: Can be Hybrid OR Remote
Connect With Draper for Future OpportunitiesIf you don't find the right posting in our Career Opportunities, you may submit your resume for future consideration.