Senior Engineer, Application Development - California, MO, United States - Conductor

Description

DRAM IO Lab is part of Samsung's Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume.

DRAM IO's vision is to solve critical bottlenecks in Cloud & Data center, Automotive, and even edge-devices by developing new approaches via high-speed interfaces, and advanced architectures.

We are an integral part of Samsung's paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing.

Location:

Hybrid, working onsite at our San Diego or San Jose, CA headquarters 3 days a week, with the flexibility to work remotely the remainder of your time.

Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design.

The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES.

Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.

Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure that the design meets or exceeds target goals.

Need to help the team to comply with the design methodologies, create and maintain design documents, and follow the release flows.

Simulate designs with state-of-the-art CAD tools
Document designs and simulation results

Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years in Electrical Engineering, Computer Science or related field preferred.

~Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design.
~ Experience in high frequency clock distribution design, implementation, and analysis.
~ Deep understanding of PPA (performance, power, and area) trade-offs.
~ Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
~ Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
~ An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
~ You're collaborative, building relationships, humbly offering support and openly welcoming approaches
~ Innovative and creative, you proactively explore new ideas and adapt quickly to change

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