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Senior Design Verification Engineer - San Diego, United States - LanceSoft
Description
Location:
San Diego, CA, (Candidate needs to work Day 1 onsite)
Experience level:
8- 15 Years
Senior ASIC Engineer role with strong experience on
System Verilog, UVM, DDR PHY / LPDDR protocol, Power aware simulations.
What You'll Be Doing:
Work involves executing complete verification project in the role of Senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspects.
What We Are Looking For:
Technical:
At-least 5+ years of experience in
System Verilog HVL.
At-least 5+ year of experience in
UVM.
Experience with VIP development primarily experienced in
DDR PHY / LPDDR protocol
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions and coverage closure.
Proficient in SVTB/UVMAnalog+Digital co-verification experience
Proficient in debug and assertions coding
Gate level simulation experience
Expert in
Power aware simulations
Make/Perl/Python
Ensure customer satisfaction.
Reporting to customer on daily or weekly progress effectively
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