Logic/RTL Design Engineer - Santa Clara, United States - Intel

Description

Job Details:

Job Description: Role and Responsibilities:In this role, responsibilities include (but are not limited to):Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

Participates in the definition of architecture and microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.

Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Follows secure development practices to address the security threat model and security objects within the design.
Works with IP providers to integrate and validate IPs at the SoC level.
Drives quality assurance compliance for smooth IPSoC handoff.


Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum


Qualifications:

Possess a Bachelor's degree in Electrical/Computer Engineering or related field and 4+ years of experience Or a Master's degree in Electrical/Computer Engineering or related field and 3+ years of experience.4+ years of RTL coding and/or IP integration experience using Verilog/SystemVerilog.2+ years prior experience in addressing LINT, CDC and Static Timing Analysis issues.2+ years prior experience with Power UPF.2+ years prior experience as IP design engineer or SOC integration engineer interfacing with IP design teams.2+ year prior experience in SOC micro-architecture (clocking, reset, power, etc) in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.

1+ year of experience in debugging complex issues in SOC verificationPreferred


Qualifications:

8+ years of RTL coding and/or IP integration experience.3+ years experience with common interfaces like DDR, PCIe, UCIe, HBM or other designs.

Understand complex SOC architecture concepts including Cache Coherency, Multi-processor interactions with NOCGood understanding of basics of PCIe architectureGood understanding of basics of DDR architectureGood integration knowledge of analog circuits and mixed signal designs.

Implement RTL in SystemVerilog, perform unit level testing, debug tests, SDC and UPF generation.
Integrate hard IP and soft IPs including industry standard and proprietary interfaces.

Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimationPerform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis.

Ensure designs are delivered on time and with the highest quality by using proper checks.
Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members.
Work with verification team for test plan/strategy to meet all functional requirements and performance.
Work with timing and physical team for timing closure and meet power and area goals.
Support project managers with effort estimations and resource planning.
Support team leader in coaching, training and development team members.
Knowledge of Synthesis/Auto P and R, Primetime, post-silicon testing, etc. are a plus.
Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.


Job Type:

Experienced HireShift:
Shift 1 (United States of America)

Primary Location:
US, California, Santa Clara

Additional Locations:

US, California, FolsomBusiness group:IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon.

We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process.

IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance

Position of TrustN/ABenefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.

Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in US, California:$144,501.00-$217,311.00Salary range dependent on a number of factors including location and experience.

Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

In certain circumstances the work model may change to accommodate business needs.


SummaryLocation:
US, California, Santa Clara; US, California, FolsomType: Full time