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    Senior Physical Design Engineer - San Diego, United States - LanceSoft, Inc.

    LanceSoft, Inc.
    LanceSoft, Inc. San Diego, United States

    3 weeks ago

    Default job background
    Engineering / Architecture
    Description

    Principal Duties & Responsibilities :


    • Implement Hierarchical blocks of the DDR/system cache subsystem running the physical synthesis with Synopsys Fusion Compiler.


    • Work with RTL designers on managing complex power intent


    • Manage timing constraints


    • Trouble shoot upf issues in synthesis


    • Run Conformal Low Power Checks on final netlist and resolve clp violations


    • Run Power Aware Conformal Logic Equivalency Check: both RTL 2 Gate and Gate 2 Gate.


    • Run STA on final netlist and support PD timing/congestion closure


    • Work with RTL designers and PD team in evaluating and executing both manual and tool generated (Conformal eco) functional eco

    Required Competencies (All competencies below are required upon entry)


    • Analytical Skills - The ability to collect information and identify fundamental patterns/trends in data. This includes the ability to gather, integrate, and interpret information from several sources.


    • Communication - The ability to convey information clearly and accurately, as well as choosing the most effective method of delivery (e.g., email, phone, face-to-face). This includes using a technically sound communication style both verbally and in writing.


    • Getting Work Done - The ability to be organized, resourceful, and planful. This includes the ability to leverage multiple resources to get things done and lay out tasks in sufficient detail. This also includes the ability to get things done with fewer resources and in less time, work on multiple tasks at once without losing track, and foresee and plan around obstacles.


    • Proficient in running Physical synthesis with Synopsys Fusion Compiler on SoC Top Level blocks with complex power intent.


    • Proficient running Cadence Conformal Low Power checks on block with complex power intent.


    • Proficient in running Cadence Conformal Power Aware Logic Equivalency Checks.


    • Proficient in running STA with Synopsys PTSI.

    Top 5 Required Skills:

    1. Physical synthesis

    2. Low Power Design

    3. STA

    4. Conformal low power

    5. Conformal Power aware logic equivalency check

    Required Education:

    Bachelor's degree in computer science, Electrical/Electronic Engineering, Engineering or related field and 6+ years of Hardware Engineering or related work experience

    -OR-

    Master's degree in computer science, Electrical/Electronic Engineering, Engineering or related work experience and 4+ of Hardware Engineering or related work experience

    -OR-

    PhD in Computer Science, Electrical/Electronic Engineering, Engineering or related field and 2+ of Hardware Engineering or related work experience

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