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- Synthesis and STA constraint development and validation at block level and top level
- Synthesis methodologies and scripts
- Static timing analysis
- Design methodology, micro-architecture, RTL
- Work with the back-end team on netlist/RTL and constraint delivery
- Work with the back-end team to develop block level and top level STA constraints.
- Master's degree in electrical engineering, computer engineering, or a related field.
- 15+ years professional experience as a hardware design engineer, SOC design engineer, hardware engineer, or related position.
- Experience must include Synthesis/STA constraint development and validation.
- Synthesis and timing check script and flow development experience is required.
- Good experience in working with back-end teams on constraint handover is highly desired.
Sr Principal Engineer - San Jose, CA, United States - SiMa Technologies
Description
Description Job Title: Sr Principal Engineer - Hardware Design Job Location: San Jose, CA Job ID: AI2300 Job Description: As a Sr Principal Engineer - Hardware Design engineer, you will help develop timing constraints and synthesis flow for 's MLSoC. Your responsibilities will include develop a framework for timing constraints development and validation and synthesis including creating guideline documents, scripts and methodologies. This means working very closely with the design team, DFT team and back-end teams. The primary design target is an SoC ASIC, with machine learning being a key component. Role & responsibilities:#J-18808-Ljbffr