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    • Physical Design Engineer - San Jose - Technical-Link N. America

    Technical-Link N. America
    Technical-Link N. America San Jose

    2 weeks ago

    Default job background
    Description

    Physical Design/Place and Route Engineer

    We are seeking an experienced Physical Design/Place and Route Engineer to join our team at Technical Link & America.

    • Mastery of Cadence Innovus PNR flow is required.
    • Proficiency in importing designs into the Virtuoso environment is essential.
    • Strong experience with physical design verification using standalone Caliber is necessary.
    • Able to create chip tops for Tape-Out (TO) packages.
    • Familiarity with bump map creation is a must.
    • Experience with LEF/DEF generation for both chip-level and block-level designs is required.
    • Familiarity with TSMC 7nm or below nodes is a plus.

    Job Requirements:

    • Cadence Innovus PNR flow expertise.
    • Virtuoso environment proficiency.
    • Caliber-based physical design verification experience.
    • Chip top creation for TO packages.
    • Bump map creation familiarity.
    • LEF/DEF generation skills for chip- and block-level designs.
    • TSMC 7nm or below node familiarity.

    Skill Enhancements:

    • Develop expertise in Cadence Innovus PNR flow.
    • Enhance proficiency in Virtuoso environment.
    • Improve physical design verification skills using Caliber.
    • Elevate chip top creation abilities for TO packages.
    • Refine bump map creation techniques.
    • Expand LEF/DEF generation capabilities for chip- and block-level designs.
    • Nurture familiarity with TSMC 7nm or below nodes.

    About the Role:

    This mid-senior level role is full-time and focuses on semiconductor manufacturing. If you have a strong background in physical design, place and route engineering, and want to work in a dynamic environment, we encourage you to apply.

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